Finite State Machines

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Finite State Machines. Resources. Sundar Rajan, Essential VHDL: RTL Synthesis Done Right Chapter 6, Finite State Machines Stephen Brown and Zvonko Vranesic, Fundamentals of Digital Logic with VHDL Chapter 8, Synchronous Sequential Circuits. Finite State Machines.

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### Finite State Machines

ECE 449 – Computer Design Lab

Resources
• Sundar Rajan, Essential VHDL: RTL Synthesis
• Done Right
• Chapter 6, Finite State Machines
• Stephen Brown and Zvonko Vranesic,
• Fundamentals of Digital Logic with VHDL
• Chapter 8, Synchronous Sequential Circuits

ECE 449 – Computer Design Lab

Finite State Machines
• Any Circuit with Memory Is a Finite State Machine
• Even computers can be viewed as huge FSMs
• Design of FSMs Involves
• Defining states
• Defining transitions between states
• Optimization / minimization
• Above Approach Is Practical for Small FSMs Only

ECE 449 – Computer Design Lab

Moore FSM (1)

Inputs

Transition

function

Next State

Present State

Memory

(register)

Output

function

Outputs

• Output Is a Function of Present State Only

ECE 449 – Computer Design Lab

Mealy FSM (1)

Inputs

Transition

function

Next State

Present State

Memory

(register)

Output

function

Outputs

• Output Is a Function of a Present State and Inputs

ECE 449 – Computer Design Lab

Moore Machine
• Describe Outputs as Concurrent Statements Depending on State Only

transition

condition 1

state 2 /

output 2

state 1 /

output 1

transition

condition 2

ECE 449 – Computer Design Lab

Mealy Machine
• Describe Outputs as Concurrent Statements Depending on State and Inputs

transition condition 1 /

output 1

state 2

state 1

transition condition 2 /

output 2

ECE 449 – Computer Design Lab

Moore vs. Mealy FSM (1)
• Moore and Mealy FSMs Can Be Functionally Equivalent
• Equivalent Mealy FSM can be derived from Moore FSM and vice versa
• Mealy FSM Has Richer Description and Usually Requires Smaller Number of States
• Smaller circuit area

ECE 449 – Computer Design Lab

Moore vs. Mealy FSM (2)
• Mealy FSM Computes Outputs as soon as Inputs Change
• Mealy FSM responds one clock cycle sooner than equivalent Moore FSM
• Moore FSM Has No Combinational Path Between Inputs and Outputs
• Moore FSM is less likely to introduce delays in critical path

ECE 449 – Computer Design Lab

Moore FSM - Example 1

0

1

0

S0 / 0

1

S1 / 0

S2 / 1

1

0

• Moore FSM that Recognizes Sequence 10

reset

ECE 449 – Computer Design Lab

Mealy FSM - Example 1
• Mealy FSM that Recognizes Sequence 10

0 / 0

1 / 0

1 / 0

S0

S1

reset

0 / 1

ECE 449 – Computer Design Lab

Moore & Mealy FSMs – Example 1

clock

0 1 0 0 0

input

S0 S1 S2 S0 S0

Moore

S0 S1 S0 S0 S0

Mealy

ECE 449 – Computer Design Lab

FSMs in VHDL
• Finite State Machines Can Be Easily Described With Processes
• Synthesis Tools Understand FSM Description If Certain Rules Are Followed
• State transitions should be described in a process sensitive to clock and asynchronous reset signals only
• Outputs described as concurrent statements outside the process

ECE 449 – Computer Design Lab

FSM States (1)

architecture behavior of FSM is

type state is (list of states);

signal FSM_state:state;

begin

process(clk, reset)

begin

if reset = ‘1’ then

FSM_state <= initial state;

else

case FSM_state is

ECE 449 – Computer Design Lab

FSM States (2)

case FSM_state is

when state_1 =>

if transition condition 1 then

FSM_state <= state_1;

end if;

when state_2 =>

if transition condition 2 then

FSM_state <= state_2;

end if;

end case;

end if; end process;

ECE 449 – Computer Design Lab

Moore FSM - Example 1

0

1

0

S0 / 0

1

S1 / 0

S2 / 1

1

0

• Moore FSM that Recognizes Sequence 10

reset

ECE 449 – Computer Design Lab

Moore FSM in VHDL

type state is (S0, S1, S2);

signal Moore_state: state;

U_Moore: process(clock, reset)

Begin

if(reset = ‘1’) then

Moore_state <= S0;

elsif(clock = ‘1’ and clock’event) then

case Moore_state is

when S0 =>

if input = ‘1’ then Moore_state <= S1; end if;

when S1 =>

if input = ‘0’ then Moore_state <= S2; end if;

when S2 =>

if input = ‘0’ then Moore_state <= S0;

else Moore_state <= S1; end if;

end case;

end if;

End process;

Output <= ‘1’ when Moore_state = S2 else ‘0’;

ECE 449 – Computer Design Lab

Mealy FSM - Example 1
• Mealy FSM that Recognizes Sequence 10

0 / 0

1 / 0

1 / 0

S0

S1

reset

0 / 1

ECE 449 – Computer Design Lab

Mealy FSM in VHDL

type state is (S0, S1);

signal Mealy_state: state;

U_Mealy: process(clock, reset)

Begin

if(reset = ‘1’) then

Mealy_state <= S0;

elsif(clock = ‘1’ and clock’event) then

case Mealy_state is

when S0 =>

if input = ‘1’ then Mealy_state <= S1; end if;

when S1 =>

if input = ‘0’ then Mealy_state <= S0; end if;

end case;

end if;

End process;

Output <= ‘1’ when (Mealy_state = S1 and input = ‘0’) else ‘0’;

ECE 449 – Computer Design Lab

Reset

w

=

1

¤

¤

A

z

=

0

B

z

=

0

w

=

0

w

=

0

w

=

1

w

=

0

¤

C

z

=

1

w

=

1

Moore FSM – Example 2: State diagram

ECE 449 – Computer Design Lab

Next state

Present

Output

z

state

w

=

0

w

=

1

A

A

B

0

B

A

C

0

C

A

C

1

Moore FSM – Example 2: State table

ECE 449 – Computer Design Lab

Moore FSM – Example 2: VHDL code (1)

USE ieee.std_logic_1164.all ;

ENTITY simple IS

PORT ( Clock, Resetn, w : IN STD_LOGIC ;

z : OUT STD_LOGIC ) ;

END simple ;

ARCHITECTURE Behavior OF simple IS

TYPE State_type IS (A, B, C) ;

SIGNAL y : State_type ;

BEGIN

PROCESS ( Resetn, Clock )

BEGIN

IF Resetn = '0' THEN

y <= A ;

ELSIF (Clock'EVENT AND Clock = '1') THEN

con’t ...

ECE 449 – Computer Design Lab

Moore FSM – Example 2: VHDL code (2)

CASE y IS

WHEN A =>

IF w = '0' THEN

y <= A ;

ELSE

y <= B ;

END IF ;

WHEN B =>

IF w = '0' THEN

y <= A ;

ELSE

y <= C ;

END IF ;

WHEN C =>

IF w = '0' THEN

y <= A ;

ELSE

y <= C ;

END IF ;

END CASE ;

END IF ;

END PROCESS ;

z <= '1' WHEN y = C ELSE '0' ;

END Behavior ;

ECE 449 – Computer Design Lab

Alternative VHDL code (1)

ARCHITECTURE Behavior OF simple IS

TYPE State_type IS (A, B, C) ;

SIGNAL y_present, y_next : State_type ;

BEGIN

PROCESS ( w, y_present )

BEGIN

CASE y_present IS

WHEN A =>

IF w = '0' THEN

y_next <= A ;

ELSE

y_next <= B ;

END IF ;

WHEN B =>

IF w = '0' THEN

y_next <= A ;

ELSE

y_next <= C ;

END IF ;

ECE 449 – Computer Design Lab

Alternative VHDL code (2)

WHEN C =>

IF w = '0' THEN

y_next <= A ;

ELSE

y_next <= C ;

END IF ;

END CASE ;

END PROCESS ;

PROCESS (Clock, Resetn)

BEGIN

IF Resetn = '0' THEN

y_present <= A ;

ELSIF (Clock'EVENT AND Clock = '1') THEN

y_present <= y_next ;

END IF ;

END PROCESS ;

z <= '1' WHEN y_present = C ELSE '0' ;

END Behavior ;

ECE 449 – Computer Design Lab

Reset

¤

w

=

1

z

=

0

¤

¤

w

=

0

z

=

0

w

=

1

z

=

1

A

B

¤

w

=

0

z

=

0

Mealy FSM – Example 2: State diagram

ECE 449 – Computer Design Lab

z

Next state

Output

Present

state

w

=

0

w

=

1

w

=

0

w

=

1

A

A

B

0

0

B

A

B

0

1

Mealy FSM – Example 2: State table

ECE 449 – Computer Design Lab

Mealy FSM – Example 2: VHDL code (1)

LIBRARY ieee ;

USE ieee.std_logic_1164.all ;

ENTITY mealy IS

PORT ( Clock, Resetn, w : IN STD_LOGIC ;

z : OUT STD_LOGIC ) ;

END mealy ;

ARCHITECTURE Behavior OF mealy IS

TYPE State_type IS (A, B) ;

SIGNAL y : State_type ;

BEGIN

PROCESS ( Resetn, Clock )

BEGIN

IF Resetn = '0' THEN

y <= A ;

ELSIF (Clock'EVENT AND Clock = '1') THEN

CASE y IS

WHEN A =>

IF w = '0' THEN y <= A ;

ELSE y <= B ;

END IF ;

ECE 449 – Computer Design Lab

Mealy FSM – Example 2: VHDL code (2)

WHEN B =>

IF w = '0' THEN y <= A ;

ELSE y <= B ;

END IF ;

END CASE ;

END IF ;

END PROCESS ;

with y select

z <= '0' when A,

z <= w when others;

END Behavior ;

ECE 449 – Computer Design Lab

State Encoding Problem
• State Encoding Can Have a Big Influence on Optimality of the FSM Implementation
• No methods other than checking all possible encodings are known to produce optimal circuit
• Feasible for small circuits only
• Using Enumerated Types for States in VHDL Leaves Encoding Problem for Synthesis Tool

ECE 449 – Computer Design Lab

Types of State Encodings (1)
• Binary – State Encoded as a Binary Number
• Small number of used flip-flops
• Potentially complex transition functions leading to slow implementations
• One-Hot – Only One Bit Is Active
• Number of used flip-flops as big as number of states
• Simple and fast transition functions
• Preferable coding technique in FPGAs

ECE 449 – Computer Design Lab

Types of State Encodings (2)

ECE 449 – Computer Design Lab

A user-defined attribute for manual

state assignment

(ENTITY declaration not shown)

ARCHITECTURE Behavior OF simple IS

TYPE State_type IS (A, B, C) ;

ATTRIBUTE ENUM_ENCODING : STRING ;

ATTRIBUTE ENUM_ENCODING OF State_type : TYPE IS "00 01 11" ;

SIGNAL y_present, y_next : State_type ;

BEGIN

con’t ...

Figure 8.34

ECE 449 – Computer Design Lab

Using constants for manual state assignment (1)

ARCHITECTURE Behavior OF simple IS

SIGNAL y_present, y_next : STD_LOGIC_VECTOR(1 DOWNTO 0);

CONSTANT A : STD_LOGIC_VECTOR(1 DOWNTO 0) := "00" ;

CONSTANT B : STD_LOGIC_VECTOR(1 DOWNTO 0) := "01" ;

CONSTANT C : STD_LOGIC_VECTOR(1 DOWNTO 0) := "11" ;

BEGIN

PROCESS ( w, y_present )

BEGIN

CASE y_present IS

WHEN A =>

IF w = '0' THEN y_next <= A ;

ELSE y_next <= B ;

END IF ;

… con’t

ECE 449 – Computer Design Lab

RTL Design Components

Data Inputs

Control Inputs

Datapath

Circuit

Control

Circuit

Data Outputs

ECE 449 – Computer Design Lab

Datapath Circuit
• Provides All Necessary Resources and Interconnects Among Them to Perform Specified Task
• Examples of Resources
• Adders, Multipliers, Registers, Memories, etc.

ECE 449 – Computer Design Lab

Control Circuit
• Controls Data Movements in Operational Circuit by Switching Multiplexers and Enabling or Disabling Resources
• Follows Some ‘Program’ or Schedule
• Usually Implemented as FSM

ECE 449 – Computer Design Lab

Control Unit Example: Arbiter (1)

reset

g1

r1

Arbiter

g2

r2

g3

r3

clock

ECE 449 – Computer Design Lab

Control Unit Example: Arbiter (2)

000

Reset

Idle

0xx

1xx

¤

gnt1

g

=

1

1

1xx

x0x

01x

¤

gnt2

g

=

1

2

x1x

xx0

001

¤

gnt3

g

=

1

3

xx1

ECE 449 – Computer Design Lab

Control Unit Example: Arbiter (3)

r

r

r

1

2

3

Reset

Idle

r

r

1

1

¤

gnt1

g

=

1

1

r

r

r

r

1

2

1

2

¤

gnt2

g

=

1

2

r

r

r

r

r

2

3

1

2

3

¤

gnt3

g

=

1

3

r

3

ECE 449 – Computer Design Lab

Arbiter – VHDL code (1)

LIBRARY ieee;

USE ieee.std_logic_1164.all;

ENTITY arbiter IS

PORT ( Clock, Resetn : IN STD_LOGIC ;

r : IN STD_LOGIC_VECTOR(1 TO 3) ;

g : OUT STD_LOGIC_VECTOR(1 TO 3) ) ;

END arbiter ;

ARCHITECTURE Behavior OF arbiter IS

TYPE State_type IS (Idle, gnt1, gnt2, gnt3) ;

SIGNAL y : State_type ;

BEGIN

PROCESS ( Resetn, Clock )

BEGIN

IF Resetn = '0' THEN y <= Idle ;

ELSIF (Clock'EVENT AND Clock = '1') THEN

CASE y IS

WHEN Idle =>

IF r(1) = '1' THEN y <= gnt1 ;

ELSIF r(2) = '1' THEN y <= gnt2 ;

ELSIF r(3) = '1' THEN y <= gnt3 ;

ELSE y <= Idle ;

END IF ;

ECE 449 – Computer Design Lab

Arbiter – VHDL code (2)

WHEN gnt1 =>

IF r(1) = '1' THEN y <= gnt1 ;

ELSE y <= Idle ;

END IF ;

WHEN gnt2 =>

IF r(2) = '1' THEN y <= gnt2 ;

ELSE y <= Idle ;

END IF ;

WHEN gnt3 =>

IF r(3) = '1' THEN y <= gnt3 ;

ELSE y <= Idle ;

END IF ;

END CASE ;

END IF ;

END PROCESS ;

g(1) <= '1' WHEN y = gnt1 ELSE '0' ;

g(2) <= '1' WHEN y = gnt2 ELSE '0' ;

g(3) <= '1' WHEN y = gnt3 ELSE '0' ;

END Behavior ;

ECE 449 – Computer Design Lab

Hands-on Session

Enough Talking Let’s Get To It!!Brace Yourselves!!

ECE 449 – Computer Design Lab

Experiment 3

Introduction

ECE 449 – Computer Design Lab

Experiment 3 – Part 1

Non-resetting detector of the sequence:

(101)+(11)+

sd

sc

sb

se

sa

Input: 00101001011101111111011011011100101

Output: 00000000000100010101000000000100000

ECE 449 – Computer Design Lab

Experiment 3 – Part 1

ARCHITECTURE Behavior OF simple IS

TYPE State_type IS (A, B, C) ;

SIGNAL y : State_type ;

BEGIN

PROCESS ( Resetn, Clock )

BEGIN

IF Resetn = '0' THEN

y <= A ;

ELSIF (Clock'EVENT AND Clock = '1') THEN

ECE 449 – Computer Design Lab

Experiment 3 – Part 2 – Bonus

Non-resetting detector of the sequence:

(001)+(1100)

SB

SC

SA

Input: 001010011100100111001001110000101

Output: 000000000001000000010000000100000

ECE 449 – Computer Design Lab

Experiment 3 – Part 2 – Bonus

English

ARCHITECTURE Behavior OF simple IS

TYPE State_type IS (A, B, C) ;

SIGNAL y : State_type ;

BEGIN

PROCESS ( Resetn, Clock )

BEGIN

IF Resetn = '0' THEN

y <= A ;

ELSIF (Clock'EVENT AND Clock = '1') THEN

ECE 449 – Computer Design Lab

Questions?

ECE 449 – Computer Design Lab