VR4121 64-BIT MICROPROCESSOR

1. VR4121 64-BIT MICROPROCESSOR โดย นางสาว พิลาวัณย์ พลับรู้การ นางสาว เพ็ญพรรณ อัศวนพเกียรติ

2. Agenda • Overview of VR4121 • VR4121 pipeline

3. Overview of VR4121

4. Introduction to VR4121 • 64 bit microprocessor in VR series manufactured by NEC. • Designed for high performance handheld portable computing devices. • Designed around the MIPS RISC architecture developed by MIPS technologies.

5. Block Diagram I/O GIU GIU LCD module OSB OSB PLL HSP HSP keyboard KIU KIU VR4120 CPU core 131/168 MHz RTC RTC LED LED LED DSU DSU PC card AIU AIU ICU ICU D/A ROM/ Flash PMU PMU PIU PIU CMU CMU Touch panel A/D BUS CONTROL UNIT BUS CONTROL UNIT EDO/SDRAM SIU SIU RS232 driver DCU DCU FIR FIR DMAU DMAU

6. VR4120 CPU core • CPU • Coprocessor 0 • Instruction cache • Data cache • CPU bus interface • Clock generator

7. CPU registers General purpose registers Multiply / divide registers 63 0 63 0 R0 = 0 HI R1 63 0 R2 LO . . . Program counter 63 0 R30 PC R31 = Link Address

8. Data format and addressing • Double word 64 bits • Word 32 bits • Half word 16 bits • Byte 8 bits VR4121 supports the little-endian order only

9. Load and store instructions Computational instructions Jump and branch instructions Coprocessor 0 instructions Special instructions Load and store instructions Computational instructions Jump and branch instructions Special instructions CPU instruction set 32 bit length instruction MIPS III 16 bit length instruction MIPS 16

10. Memory Management Unit : MMU • Virtual addresses are translated into physical addresses using an on-chip TLB. • The on-chip TLB is a fully-associative memory that holds 32 entries. • These pages can have five different sizes, 1 K, 4 K, 16 K, 64 K, and 256 K, and can be specified in each entry.

11. Cache memory (1) VR4120 CPU core Main memory Cache controller I-cache D-cache

12. Cache memory (2) • The instruction cache is 16 Kbytes and the data cache is 8 Kbytes. • The line size for the instruction/data cache is 4 words (16 bytes). • The VR4120 CPU core uses write-back policy.

13. Conclusion : Features of VR4121 • Employs 64-bit RISC CPU Core (VR 4120 equivalent) • Internal 64-bit data processing. • Optimized 6-stage pipeline. • On-chip cache memory Instruction cache: 16 Kbytes, Data cache: 8 Kbytes. • Address space Physical address space: 32 bits, Virtual address space: 40 bits.

14. Conclusion : Features of VR4121 • Memory controller (supports ROM, EDO-type DRAM, SDRAM, SROM, and flash memory) • Keyboard, Touch panel, audio interface. • DMA, interrupt controller. • Serial interface. • General-purpose ports. • IrDA interface.

15. Conclusion : Features of VR4121 • Effective power management features, which include the following four operating modes:Full-speed mode, Standby mode, Suspend mode, Hibernate mode. • External input clock: 32.768 kHz, 18.432 MHz (for internal CPU core and peripheral unit operation), 48 MHz(dedicated for IrDA interface)

16. VR4121 Pipeline

17. IF RF EX DC WB VR4121 Pipeline • Pipeline Stages • The pipeline is controlled by PClock. • Pipeline in MIPS III(32-bit length) instruction mode • The execution of each instruction takes at least 5 PCycles. Pcycle PClock Stage

18. IF IT RF EX DC WB VR4121 Pipeline • Pipeline in MIPS16 (16-bit length) instruction mode • The execution of each instruction requires at least 6 PCycles. Pcycle PClock Stage

19. Delay in Pipeline • Branch Delay, a one-cycle branch delay occurs when: • Target address is calculated by a jump instruction. • Branch condition of branch instruction is met and then logical operation starts for branch-destination comparison. • Load Delay • A load instruction that does not allow its result to be used by the instruction immediately following is called a delayed load instruction.

20. Branch (Branch delay slot) Target Branch delay Branch Delay (in MIPS III Instruction Mode) IF RF EX DC WB IF RF EX DC WB IF RF EX DC WB Delay in Pipeline

21. (Branch delay slot) Target Branch delay IF IT RF EX DC IF IT RF EX DC IF IT RF EX DC WB WB WB Branch Delay (in MIPS 16 Instruction Mode) Delay in Pipeline Branch

22. Faults Exceptions Interlocks Abort Stall Slip Interlock and Exception Handling • Pipeline flow is interrupted when cache misses or exceptions occur, or when data dependencies are detected.

23. Exception IF RF IF 1 2 IF RF EX DC WB IF RF EX DC WB IF RF EX DC WB IF RF EX DC WB Exception vector Discard stage Interpret Exception conditions • Example: Interrupt exception, ITLB exception. • When an exception condition occurs, the relevant instruction and all those that follow it in the pipeline are cancelled.

24. Stall conditions • Example: Instruction TLB Miss and Instruction Cache Miss. • When a stall occurs, the processor will resolve the condition and then the pipeline will continue.

25. IF RF EX EX DC DC DC WB WB WB IF RF EX DC DC EX EX EX DC WB RF RF RF EX DC IF RF EX DC WB IF RF RF WB WB WB Stall Conditions Data Cache Miss Stall 1 2 3 1. Detect data cache miss 2. Starting moving data cache line to write buffer 3. Get last word into cache and restart pipeline

26. IF RF EX EX DC DC DC WB WB WB IF RF EX DC DC EX EX EX DC WB RF RF RF EX DC IF RF EX DC WB IF RF RF WB WB WB Stall conditions Cache Instruction Stall 1 2 1. Cache instruction start 2. Cache instruction complete

27. Slip conditions • If all of the source operands are available (either from the register file or via the internal bypass logic) and all the hardware resources necessary to complete the instruction will be available whenever required, then the instruction "run"; otherwise, the instruction will "slip". • Example: Load Data Interlock and MD Busy Interlock.

28. WB DC WB IF RF EX DC WB IF RF EX DC DC2 IF RF RF RF EX IF RF EX DC DC2 Slip conditions • Load Data Interlock Load A Load B Bypass WB Add A,B 1 1 2 1. Detect load interlock 2.Get the target data

29. DC DC WB WB EX EX IF RF EX DC WB IF RF EX EX EX IF RF EX EX EX Slip conditions MD Busy Interlock MUL/DIV Multiply/Division opration Bypass MFHI/MFLO 1 1 1 1 2 1 . Detect MD busy Interlock 2. Get target data

30. Bypassing • Operand bypass allows an instruction in the EX stage to continue without having to wait for data or conditions to be written to the register file at the end of the WB stage.

31. VR Series Supported Instruction

32. End of the presentation... Any Question ????