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Sundance PowerPoint Presentation

Sundance

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Sundance

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  1. Sundance Multiprocessor Technology Ltd High-tech DSP solutions. Giving you the freedom to design SYSTEM CONFIGURATION

  2. CARRIERBOARD Host Comport TIM1 TIM2 TIM3 TIM4 PCI HOST Master Global bus Reset Config line PCI HOST/Carrier Board

  3. Reset Power-up TIMn FPGA FPGA Init bootloader Config. load F L A S H DSP bitstreams Userdata Run application DSP module bootloader bitstreams application Userdata Communication resources

  4. Reset Power-up TIMn FPGA FPGA Init bitstream Config. load P R O M Xilinx Parallel Cable IV JTAG CPLD Run FPGA module with PROM Communication resources

  5. Reset Power-up FPGA Init Config. load Run FPGA modulevia comport TIMn FPGA ComPort Transmitter Communication resources ComPort CPLD bitstream

  6. TIM1 TIM2 FPGA FPGA Links ComPort bitstream HOST F L A S H CPLD or MSP430 DSP TIMconnector TIMconnector Reset System with Host Communication resources Communication resources

  7. TIM1 FPGA Links ComPort bitstream HOST F L A S H DSP TIM connector TIM connector Config Reset Reconfiguring with the Config line TIM2 FPGA Communication resources Communication resources CPLD or MSP430

  8. Reset Power-up - The PROGRAM and INIT pins are both driven Low by the FPGA. - PROGRAM goes High and INIT goes High a short time later. The device can remain permanently in this state if either PROGRAM or INIT are held Low. FPGA Init - After INIT has gone High, the mode pins [M2..M0] are sampled on the rising edge of CCLK. Config. load - The global reset signals are toggled when the DONE pin goes High. Run Configuration sequence Slave SelectMap modeFPGA configuration