Superscalar Processors by. Sherri Sparks. Overview. What are superscalar processors? Program Representation, Dependencies, & Parallel Execution Micro architecture of a typical superscalar processor A look at 3 superscalar implementations Conclusion: The future of superscalar processing.
Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author.While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server.
L2: mov r3,r7
L3: add r6,r6,1
Blocks are issued are initiated into the “window of execution”.
Parallel Execution Method Summarized in 5 phases:
1. Instruction Fetch & Branch Prediction
2. Decode & Register Dependence Analysis
3. Issue & Execution
4. Memory Operation Analysis & Execution
5. Instruction Reorder & Commit
1. Recognizing that in instruction is a conditional branch
2. Determining the branch outcome (taken or not taken)
3. Computing the branch target
4. Transferring control by redirecting instruction fetch (as in the case of a taken branch)
STEP 1: Recognizing Conditional Branches
STEP 2: Determining Branch Outcome
STEP 3: Computing Branch Targets
branch target = program counter + offset
EX: Branch Target Address Cache used in PowerPC 604
STEP 4: Transferring Control
source operands for an operation.
1. The state of the machine is saved in a history buffer. Instruction update the state of the machine as they execute and when there is a problem, the state of the machine can be recovered from the history buffer. The commit phase gets rid of the history state that’s no longer needed.
2. The state of the machine is separated into a physical state and a logical state. The physical state is updated in memory as instructions complete. The logical state is updated in a sequential order as the speculative status of instructions is cleared. The speculative state is maintained in a reorder buffer and during the commit phase, the result of an operation is moved from the reorder buffer to a logical register or memory.
1. By increasing the likelihood that a group of instructions can be issued simultaneously
2. By decreasing the likelihood that an instruction has to wait for the result of a previous instruction