Design of 4-bit ALU. Ashwini Nanjappa Sravani Sanapala Vanita Ramaswamy Advisor: Dr.David Parent Fall 2004. Agenda. Abstract Introduction Why Simple Theory Project Details Block Diagram Schematics Layout Verification: DRC, Extract, LVS Simulation Results Cost Analysis Conclusion.
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Advisor: Dr.David Parent
Function Table for ALU
A load of 20fF is assumed as the load for long path calculation from DFF.
Long Path Calculation(Arithmetic Unit)
τPHL=5ns/(13+4)=0.29ns for each logic level
Project Details Cont’d
The inputs (A,B,CIN) and select lines (M,S0,S1)are set for worst case.
200 Mhz clock
Area: 333x412 μm2
The project meets all the given specifications
This design concept can be a building block for higher bit ALU ex. 16-bit, 32-bit…Conclusion