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Embedded Algorithm in Hardware : A Scalable Compact Genetic Algorithm

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Embedded Algorithm in Hardware : A Scalable Compact Genetic Algorithm. Prabhas Chongstitvatana Chulalongkorn University. What is Genetic Algorithms.

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## Embedded Algorithm in Hardware : A Scalable Compact Genetic Algorithm

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### Embedded Algorithm in Hardware: A Scalable Compact Genetic Algorithm

Prabhas Chongstitvatana

Chulalongkorn University

What is Genetic Algorithms
• GA is a probabilistic search procedure to obtain solutions starting from a set of candidate solutions, using improving operators to “evolve” solutions. Improving operators are inspired by natural evolution.
Characteristics of GA
• Survival of the fittest.
• The objective function depends on the problem.
• GA is not a random search.
GA pseudo code

GA

initialise population P

while not terminate

evaluate P by fitness function

P' = selection recombination mutation P

P = P‘

terminating conditions:

1. found satisfactory solutions

2. waiting too long

Simple Genetic Algorithm
• represent a solution by binary string {0,1}*
• selection:

chance to be selected is proportional to its fitness

• recombination

single point crossover

Genetic Operators

recombination

select a cut point cut two parents, exchange parts

AAAAAA111111

AA AAAA 11 1111cut at bit 2

AA111111AAAAexchange parts

mutation

single bit flip

111111 --> 111011 flip at bit 4

What problem GA is good for?
• Highly multimodal functions
• Discrete or discontinuous functions
• High-dimensionality functions, including many combinatorial ones
• Nonlinear dependencies on parameters
• (interactions among parameters) -- “epistasis”
• Often used for approximating solutions to NPcomplete
1998 Synthesis of Synchronous Sequential Logic Circuits from Partial Input/Output Sequences

.

Two-Horn Chameleon (Bradypodion fischeri ssp.) in the Usambara mountains, Tanzania

• Fabricate on FPGA, runs about 1,000 times faster than the software executing on a workstation.
Scalable Compact Genetic Algorithm in Hardware

Jewajinda, Y. and Chongstitvatana, P. 2006

Pseudocode of the normal CoCGA cell
• Generate two individual from the vector
• Let them compete
• Update the probability vector toward better one and lncrement Confidence Counter
• Check if cc is incremented then Send p and cc to the group leader cell
• Check if the vector has converged else goto step 1
• probability vector represents the final solution
Pseudocode of the group leader
• Check if cc of each neighbor is updated
• Select the highest cc of all neighbors
• Update p, with pcc with ccmax
• Update new updated p , to all normal Cell for each neighbor cell of leader cells
• Check if the vector has converged else goto step 1
• p , represents the final solution
Speedup

SPEEDUP COMPARISON BETWEEN CGA AND COCGA IN TERM OF MACHINE CYCLES (ONE MACHINE CYCLE IS EQUIVALENT To FOUR CLOCK CYCLES)

References
• Jewajinda, Y. and Chongstitvatana, P., "FPGA-based Online-learning using Parallel Genetic Algorithm and Neural Network for ECG Signal Classification," Proc. of ECTI Conf., 19-21 May 2010, Chiengmai, Thailand. (Best paper award)
• Jewajinda, Y. and Chongstitvatana, P.,"FPGA Implementation of a Cellular Univariate Estimation of Distribution Algorithm and Block-based Neural Network as an Evolvable Hardware", IEEE Congress on Evolutionary Computation, Hong Kong, June 1-6, 2008, pp.3365-3372.
• Jewajinda, Y. and Chongstitvatana, P., "A Cooperative Approach to Compact Genetic Algorithm for Evolvable Hardware", IEEE World Congress on Computational Intelligence, Vancouver, Canada, July 16-21, 2006, pp.2779-2786.
• Niparnan, N. and Chongstitvatana, P., "An improved genetic algorithm for the inference of finite state machine", IEEE Int. Conf. on Systems, Man and Cybernetics, Vol.7, 2002, pp. 340-344, Tunisia, 6-9 Oct, 2002.
• Aporntewan, C. and Chongstitvatana, P., "A Hardware Implementation of the Compact Genetic Algorithm", IEEE Congress on Evolutionary Computation, Seoul, Korea, May 27-30, 2001, pp.624-629.
• Aporntewan, C., and Chongstitvatana, P., "An on-line evolvable hardware for learning finite-state machine", Proc. of Int. Conf. on Intelligent Technologies, Bangkok, December 13-15, 2000, pp.125-134.
prabhas@chula.ac.th
• www.cp.eng.chula.ac.th/faculty/pjw/