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Advancements in Clockless Readout Systems for FPIX Testing at Columbia University

This report details the development and validation of a clockless readout concept for FPIX testing, under the direction of D. Winter at Columbia University. Key components include the modified “Proto-ROC” and “Proto-FEM” boards, which demonstrate remote data readout via fiber optic technology. The setup achieved data sampling rates of 80 MBytes/sec at 140 MHz, successfully validating its operational capabilities. Future enhancements include an optical transceiver and further refinements on the ROC board design, aimed at enabling users to interact with FPIX chips effectively.

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Advancements in Clockless Readout Systems for FPIX Testing at Columbia University

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  1. Nevis FVTX Status Dave Winter 8 June 2006 Bruce, hard at work.

  2. After Bill’s “Retirement” I know of a soldering iron with Bill’s name on it… W.A. Zajc D.Winter/Columbia University

  3. Nevis FVTX test setup • Goal: test readout concept(s) • Clockless readout • Remote data readout via fiber • Understand how to interact with FPIX • Current setup • “Proto-ROC”, “Proto-FEM”, PC, FPIX test board • Modified original Knapp test board to mate with FPIX test board D.Winter/Columbia University

  4. Test-stand Topology “proto-ROC” PCI Card (“proto-FEM”) RAM PC Optical transceiver Optical transceiver FPGA FPGA Under construction Details of each component on slides that follow… FPIX Board D.Winter/Columbia University

  5. FPIX Test Board • Single FPIX chip, no sensor • Receives power from proto-ROC board D.Winter/Columbia University

  6. “Proto-ROC” Test Board One copy modified to provide connection and power to FPIX test board Motorola DSP MC56309 JTAG port for Altera • EPC2 Serial EPROM • 2 Mb 80 MHz xtal • Altera Cyclone EP1C3T144C7 • 144 pins JTAG/Debugger port for DSP Twinax connecter header D.Winter/Columbia University

  7. “Proto-FEM” PCI Card CYP15G0101DXB serdes JTAG port for Altera 80 MHz xtal • CY7C1354B Pipelined SRAM • 256k x 36bits Altera ACEX EP1K50QC208-1 • Agilent HFBR 53A3DEM • 850 nm multimode 32-bit 33 MHz PCI standard D.Winter/Columbia University

  8. PCI Board in action Fiber connected in loop back configuration D.Winter/Columbia University

  9. Status • Validated concept of clockless readout from FPIX board using proto-ROC board • Samples Fast-data out from FPIX at 4x freq • Tested with fast clock of 140 MHz • BCO can be anything, most likely 20 to 30 MHz, though we don’t know the upper limit • Basic operation of PCI board established • User code on PC allows basic interaction • Read/write PCI registers, send data to PLD • Rudimentary loop back operation performed • Data read from RAM • Sent to fiber • Received from fiber • Received data written to RAM • Rates of 80 MBytes/sec achieved • PLD logic currently in a state of debugging • Layout for next generation of “ROC” board made • Sent to fabricator • Includes optical transceiver and serdes • Contains power and pulser for FPIX • Ready (fab+logic) in ~ 1 week • Complete system will enable user to send FPIX commands from the PC, get replies and data back into the PC D.Winter/Columbia University

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