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Computer Architecture Principles Dr. Mike Frank

Computer Architecture Principles Dr. Mike Frank. CDA 5155 Summer 2003 Module #3 Hardware Description Languages. Module #3 Outline. Introduction to Hardware Description Languages: Pseudocode Register Transfer Languages VHDL (VHSIC HW Description Language) Verilog HDL

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Computer Architecture Principles Dr. Mike Frank

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  1. Computer Architecture PrinciplesDr. Mike Frank CDA 5155Summer 2003 Module #3Hardware Description Languages

  2. Module #3 Outline Introduction to Hardware Description Languages: • Pseudocode Register Transfer Languages • VHDL (VHSIC HW Description Language) • Verilog HDL • AHPL (A Hardware Programming Language)

  3. Why HDLs? • Compared to schematic diagrams or netlist files, they can be: • More standardized & portable. • Easier to create. • More concise. • Easier to comment. • Easier to read. • Faster to simulate. • And, full manufacturable schematics/layouts can be automatically generated from HDLs by logic synthesis & place-and-route tools.

  4. Register Transfer Language • Often informal (pseudocode-like). • Often used to specify semantics of machine instructions • such as in an ISA specification, or • a pu programmer’s reference manual. • Micro-instructions (in microprogrammed architectures) often correspond to single statements in an RTL. • Don’t confuse hardware-level RTLs w. the “register transfer language” in GCC • An intermediate language btw. C code & assembly.

  5. RTL Statements: Register Copy [Cf. Carpinelli, ch. 5.] • Syntax: XY • Semantics: • On every active (e.g. rising) clock edge, copy the contents of register Y to register X. • Example schematic implementation: clk Registers could be multi-bit.Instead of just Y we could have a function, like Y+Z. D Y Q D X Q

  6. RTL sts. cont.: Conditional Copy • Syntax: IF  THEN XY or : XY • Semantics: • On every active clock edge, if condition (signal)  is true (logic 1), then copy register Y to reg. X.” • Ex. Impl.: clk  could be any Boolean function of register valuese.g. Z==W+1 D Y Q D X Q LD 

  7. RTL: Parallel Operations • Syntax: : XY, YZ • Semantics: • When  is true, copy Y to X and Z to Y (simultanously). • Beware of write conflicts! clk D Z Q D Y Q LD D X Q LD 

  8. RTL: Implicit multiplexers • Consider the following: : XY : XZ • What if  and are both highsimultaneously? • Mutually exclusive conditions: ´: XY : XZ D X Q LD 0 1 S YZ  

  9. RTL: Ranges of bits • Syntax: X(3:1)  Y(2:0) • Semantics: Bits 3,2,1 of X are copied from bits 2,1,0 of Y, respectively. • Another example:X(3:0)  X(2:0),X(3)(Copy bits 3,2,1,0 from bits 2,1,0,3.I.e. rotate bits in X(3:0) left by 1 position.)

  10. More Complex RTL Examples • Going through Carpinelli sections 5.2, 5.3.(Entire chapter 5 will be available online.) • At this point we switch over to the document camera…

  11. Hardware Description Languages • VHSIC HDL (VHDL) (IEEE standard 1076) (Carpinelli §5.4, misc books) • Verilog HDL (IEEE std. 1364). (See web.) • Update on “Verilog-VHDL” wars... • Verilog: Most popular, faster sims, better tools, easier to learn, faster to code... • VHDL: More tightly-structured language, higher-level, government standard, required for all defense contracts. • Verilog:VHDL :: C:Ada ? • Standards bodies Open Verilog International and VHDL International have merged  accellera.org

  12. VHDL (VHSIC HDL) • “VHSIC Hardware Description Language", M.R. Shahdad et al, IEEE Computer 18(2):94-103 (Feb 1985). • IEEE Standard 1076 (1993). • Resources that we will make available: • Various web links • Carpinelli ‘01, section 5.4. • Murdocca ‘00, section 6.4. • Naylor & Jones ’97, Rushton ’95, Baker ‘93 • More document camera stuff...

  13. Elements of VHDL • entity – Specifies HW interface (≈ Java interface) • Think of it as an empty chip package, or as an empty circuit board enclosure, w. I/O ports already installed • Comes with a set of named I/O pins of different types • architecture – Implements an interface, as a set of interconnected sub-components. (≈ Java class) • Think of a printed circuit board design, or a block diagram of an IC, with blank boxes for sub-modules • component– Template for plugging in sub-components into an architecture. (≈ interface variable) • Like a type of empty chip socket, that can be replicated many times & placed on a circuit board continued…

  14. Elements of VHDL, cont. • configuration– For a given architecture of an entity, selects which entity/architecture pairs will be used for each component. • ≈ a call a class’s constructor to assign class instances of specific types to its interface variables • Like going through empty sockets of a board, selecting what packaged chip to use in each one. • Only a configuration can actually be simulated. • package– Module, collection of related declarations (components, datatypes, etc.). (≈ Java package) • process– Stateful, concurrently running, event-driven sequences of operations.

  15. Verilog HDL • No slides yet. • FAQs / standards linked from class website.

  16. AHPL • = “A Hardware Programming Language” • A microprogramming language. • Murdocca section 6.3 (document camera). • Will be made available online.

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