Computer Architecture Principles Dr. Mike Frank

1. Computer Architecture PrinciplesDr. Mike Frank CDA 5155Summer 2003 Module #4 Market & Technology Trends

2. Upcoming Material • H&P chapter 1 - Fundamentals: Performance, quantitative design. • Technology trends, 1st-order scaling laws • Cost, yield, and fault-tolerance • Performance measurement and benchmarks • Quantitative design • Generalized Amdahl’s law • Next: Begin ISA design (ch. 2).

3. H&P Chapter 1:Fundamentals of Computer Design • 1.1. Introduction • 1.2. The Changing Face of Computing • 1.3. Technology Trends • 1.4. Cost, Price, and Their Trends • 1.5. Measuring & Reporting Performance • 1.6. Quantitative Princ. of Computer Design • 1.7. Performance & Price-Performance • 1.8. Power Consumption & Efficiency • 1.9-1.11 End material

4. 1.1. Introduction Key points to remember (from lecture 1): • General Moore’s Law trend in recent decades: • Computer performance increases @ ~50% per year • Reflects improvements in raw Si transistor ops/sec/chip • Continuing architectural innovations generally required to harness improving raw parallel HW performance for faster performance on old serial ISAs. • Eventually, serial programming models may hit a wall. • Someday, different programming models may be introduced that scale up more easily with technology improvements.

5. Raw technologyperformance (gate ops/sec/chip):Up ~55%/year Microprocessor Performance Trends

6. 1.2. The Changing Face of Computing Key points: • Historical evolution of industry dominance: • mainframes  minicomputers  PCs • Now, 3 distinct major markets: desktop, server, embedded • Different requirements for each • Each uses commodity microprocessors • Task of the computer designer • ISA, organization, microarchitecture, hardware

7. Major Market Segments • Desktop Computing • ~$1,000 PCs to $10,000 Workstations • Critical metric: Price-performance (esp. graphics) • performance per unit price, drives leading-edge • Servers • ~$10K to $1M • Availability, scalability & throughput critical • Embedded Systems • $1 (toy) to $100,000 (network router) • Real-time, application-specific performance • Small memory footprint, low power

8. Embedded Solutions • Common solutions for custom hardware: • ASIC (Application-Specific Integrated Circuit) • Custom VLSI chips integrated from standard cells • FPGA (Field-Programmable Gate Array) • Custom circuits dynamically loaded from firmware • Many embedded systems are mostly just SW running on one or more of: • On-chip embedded processor core • e.g. MIPS, ARM, etc. • COTS embedded processor • Commercial Off-The-Shelf, usu. a packaged chip • DSPs (Digital Signal Processor) • A microprocessor specialized for signal-processing tasks

9. 2nd edition, fig. 1.2 (replace w. 3rd ed., fig. 1.4)

10. 1.3. Technology Trends Key points: • Different rates of improvement in different components affect architectural decisions. • E.g., electrical buses vs. optical switches on board • Scaling of transistors, wires, power • Local connectivity, low power increasingly favored

12. (Source: ITRS 2000 Update)

13. Technology Scaling: Notation • Historically, device feature length scales have decreased by ~12%/year. • So: feature length 0.88year :  • 1/length (1/0.88)year1.14 year : (up 14%/year) • Meanwhile, typical die diameters have increased by ~2.3%/year. • Diameter  1.023year :  • 1/Diameter  

14. Some 1st-order Semiconductor Scaling Laws • Voltages V (due to punch-through effects) • Long-term: • Temperature T? (prevents leakage) • Resistance: • Fixed-shape wire: R  l/wt  / =  • Thin cross-chip wire: R / =  • Capacitance: • Fixed-shape structure: C  lw/s  / =  • Per unit wire length: C  1 (constant) • Cross-chip wire: C   • Per unit area: C  1/s  

15. Charges & Currents • Charges & fields: • Charge on a structure: Q = CV   • Surface charge density: Q/A  1 • Electric field strengths: E = V/l  1 • Currents: • Peak current densities: J = E/  1 • Peak current in a wire: I = JA   • Channel-crossing times: t=l/v   (v  200 kmph) • Current in an on-transistor: I = Q/t  / =  • Effective on-resistance: R = V/I  / = 1 Or faster w.strained Si 5-25 kΩ typical

16. Delay Scaling • Charging time delay t  RC : • Through fixed shape conductor: RC   = 1 • Via cross-die thin wire: RC  · = up 50%/yr! • Through a transistor: RC  1· =  • Implications: • Transistors increasingly faster than long thin wires. • Even becoming faster than fixed-shape wires! • Local communication among chip elements is becoming increasingly favored!

17. Performance scaling • Performance characteristics: • Clock frequency for small, transistor-delay-dominated local structures: f  1/t   (up 14%/yr) • Transistor density (per area): d = 1/ =  • Chip area: A   • Total raw performance (local transitions / chip / time): R = fd A =  = 1.55year • Up 55%/year! • Nearly doubles every 18 months (Moore’s Law).

18. Energy and Power • Energy: • Energy on a given structure: E CV2  2 = 3 • Energy per-area: EA CV2/A 3/2 =  • Energy densities: EA/thickness  /  1 • Per-area power: PA = EAf   = 1 • Power per die: P = PAA   (up ~5%/year)