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Carbon Group Manycore Directions

Carbon Group Manycore Directions. Angstrom Meeting 2008/02/28. High-Level Goals. Investigate how to scale computer systems to 1000+ cores on a single chip Architecture OS and System tools (debuggers, compilers). Architectural Improvements. On-chip Networks Topologies

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Carbon Group Manycore Directions

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  1. Carbon Group Manycore Directions Angstrom Meeting 2008/02/28

  2. High-Level Goals • Investigate how to scale computer systems to 1000+ cores on a single chip • Architecture • OS and System tools (debuggers, compilers)

  3. Architectural Improvements • On-chip Networks • Topologies • On-chip link Compression • Grain Size • How large/wide of a core • Cache to core ratio • Memory • Multicore in Memory • Scalable cache coherence

  4. Multicore in Memory Cores on one chip Cores on one chip Multicore Memory Bandwidth Gap Chip Memory (Pin) Bandwidth Off-chip Memory Bandwidth Per Core Time (Year) Time (Year) • 1MB • KB Line Size • Software Managed Memory -- DRAM • 100’s KB • 100’s B Line Size • Hardware Managed Cache -- SRAM Processor

  5. Carpool Lane Networks [1] • Large mesh networks require many hops to route a packet (high latency) • On-chip networks have plentiful wiring resources • Add long distance “carpool lanes” to mesh networks. “Carpool lanes” 2D Mesh With 2x Carpool Lanes [1] Extension of Express Lane Work by Bill Dally et.al.

  6. OS Improvements • Algorithmically refactor OS design by purpose into spatially distributed cooperating sub-services • Dedicate processors to OS / System Service servers • Define interface to allow programs to express thread affinity and communication affinity

  7. PCIe Bridge PCIe Bridge TILE64 GbE TILE64 GbE DRAM DRAM TILE64 TILE64 DRAM DRAM GbE GbE PCIe Bridge PCIe Bridge Shared Infrastructure • 1000+ core software simulator (in progress) • Pin based • Application level • Tilera 64 core development board (we have one) • Future Prototype 256-core Tilera based system Tilera 64 core dev. board Proposed 256 Core Prototype

  8. Questions we have • What characteristics do your applications have? • Can hardware enable new programming models? • Can hardware enable new OS paradigms?

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