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output depends on state and input. typically edge-triggered D flip-flops. V. Sequential network design. State-machine structure (Mealy). V. Sequential network design. output depends on state only. typically edge-triggered D flip-flops. State-machine structure (Moore).

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state machine structure mealy

output depends onstate and input

typically edge-triggered D flip-flops

V. Sequential network design

State-machine structure (Mealy)
state machine structure moore

V. Sequential network design

output dependson state only

typically edge-triggered D flip-flops

State-machine structure (Moore)
slide3

V. Sequential network design

D

S

Q

Q

Q

R

J

C

C

C

Q’

Q’

Q’

K

Q

J K q

Q

S R q

Q

0 0 0

0 0 1

0 1 0

0 1 1

0

1

0

0

D q

0 0 0

0 0 1

0 1 0

0 1 1

0

1

0

0

0 0

0 1

1 0

1 1

0

0

1

1

1 0 0

1 0 1

1 1 0

1 1 1

1

1

1

0

1 0 0

1 0 1

1 1 0

1 1 1

1

1

--

--

SR

q

00 01 11 10

0

1

d

1

1

d

1

Q = S + R’q

D

S R

J K

q Q

q  Q

q  Q

0 0

0 1

1 0

1  1

0  0

0 1

1 0

1  1

0  0

0 1

1 0

1  1

0

1

0

1

0 d

1 0

0 1

d 0

0 d

1 d

d 1

d 0

Flip Flop : summary

D Flip flop

S-R Flip flop

J-K Flip flop

q : Current state

Q : Next state

Characteristic

Table

Characteristic

Equation

JK

q

00 01 11 10

Q = D

0

1

1

1

1

1

Q = Jq’ + K’q

Transition Table

(Excitation Table)

slide4

V. Sequential network design

Flip Flop : summary

Characteristic table : For each input and state combination, define the

next state of the flip flop

Characteristic equation: Define the next state (Q) as a function of current state

and input to the flip flop

Transition table (excitation table): For each transition type,

define the inputs that cause the transition

slide5

V. Sequential network design

Major design steps

Step 1: Start from state diagram or word description

Step 2: Construct a State/Output table

Moore machine: one output per state (one output column)

Mealy machine: One output per state and for each input combination (one output column per input combination)

Step 3: Reduce the number of states in State/output table by removing redundant states (a state is redundant if for the same input combinations) it has the same next state and output as another state.

Step4: Encode the states in binary (for n states, log2n bits are required). Each bit in the code represents a flip flop.

Step5: Substitute corresponding binary codes to states in the State/Output table

Step6: Separate the state table into flip flop next state maps (one map for each bit or flip flop)

Step7: Use the flip flop next state map to derive flip flop excitation maps (this step depends on the type of flip flop used in the design)

Step8: Use the flip flop excitation maps to determine excitation equations for the flip flop (these equations define the input logic of the flip flop)

Step 9: Use the State/Output table to define the output logic circuit

Step10: Draw the circuit, including flip flop, flip flop input circuits and output circuit.

v sequential network design
V. Sequential Network Design

Example 1

Step1: Problem Description (Word description)

Design a sequential machine that detects a 01 sequence. The detection of sequence sets the output, Z=1, which is reset (Z=0) only by a 00 input sequence

Note: The input is scan one bit at a time

v sequential network design7
V. Sequential Network Design

Example 1: STEP 1

Step1: State Transition Diagram of the sequential machine:

Recall that a State Transition Diagram consists of :

  • States (representated by circles)
  • Transitions (represented as arcs) between states
  • Transitions are labelled by input that cause them
  • Output are associated with
    • input labels (MEALY MACHINE)
    • State labels (MOORE MACHINE)
v sequential network design8

0/0

1/1

B

C

1/1

1/0

A

0/0

0/1

State Description:

A : initial state (sequence does not begin)

B : 0 is detected, expecting a 1

C : 01 sequence detected, output set

to 1

V. Sequential Network Design

Example 1: STEP1

State diagram of example 1 (Mealy Machine):

Must detect a 00 to reset output to 0

First 0 detected, go to B to wait for second 0

v sequential network design9

0/0

1/1

A

C

0/0

1/1

B

0/1

1/0

State/Output table (Mealy Machine)

Output

NS

CS

X=0

X= 1

X=0

X= 1

A B A

0 0

B B C

0 1

C B C

1 1

V. Sequential Network Design

Example 1: STEP 2

State/Output table

  • For each (current state, input) pair, specify:
  • Next State
  • Output
v sequential network design10

State diagram (Moore Machine):

0

1

1

B,0

A,0

C,1

1

0

1

0

D,1

0

V. Sequential Network Design

Example 1: STEP2

A: Waiting for start of sequence 01 and output 0

B: 0 is detected, wait for 1 and output 0

C: Sequence 01 is detected, output 1 and wait for 00 to reset output

  • D: Start of 00 is detected; wait for the final 0 to reset output
  • when we get 0, go to B and output 0
  • When we get 1, go back to C to wait for 00 sequence
v sequential network design11

0

1

1

B,0

A,0

C,1

1

0

1

0

D,1

0

V. Sequential Network Design

Example 1: STEP 2

State /Output Table:

NS

Output

CS

X=0

X= 1

A B A

0

B B C

0

C D C

1

D B C

1

v sequential network design12
V. Sequential Network Design

Example 1: STEP 3

Reduce the number of states in STATE/OUTPUT table:

NO Redundant states in example 1

State /Output Table:

NS

CS

Output

X=0

X= 1

Output does not

Depend on input X

A B A

0

B B C

0

C D C

1

D B C

1

v sequential network design13
V. Sequential Network Design

Example 1: STEP 4

State Assignment: Encode the different states

  • There are 3 states  We need two States Variable y1 and y0
  • y1 is the leftmost bit (Flip flop 1)
  • y0 is the rightmost bit (Flip flop 0)

One possible state assignment:

A  00, B  01, C  10 : State code 11 is not used (don’t cares …)

There are many more state assignments:

For example, We could use the following assignments

A  11, B  10, C 01 : State code 00 is not used (don’t cares …)

A  10, B  11, C 00 : State code 01 is not used (don’t cares …)

v sequential network design14

NS

Output

CS

X=0

X= 1

X=0

X= 1

A B A

0 0

B B C

0 1

C B C

1 1

State/Output table (Mealy Machine)

NS

Output

CS

X=0

X= 1

X=0

X= 1

00 01 00

0 0

01 01 10

0 1

Unused state code

10 01 10

1 1

11 dd dd

d d

V. Sequential Network Design

Example 1: STEP 5

Substitute State Codes in the State/output table

State assignment:

A  00, B  01, C  10

v sequential network design15

State/Output table (Mealy Machine)

NS

Output

CS

X=0

X= 1

X=0

X= 1

y1 (flip flop 1)

00 0100

0 0

y0 (flip flop 0)

01 0110

0 1

10 0110

1 1

11 dddd

d d

Flip flop 1

Flip flop 0

Current

Next state Y0

Current

Next state Y1

X

X

(y1y0)

(y1y0)

0

1

0

1

00 10

00 00

01 10

01 01

10 10

10 01

11 dd

11 dd

V. Sequential Network Design

Example 1: STEP 6

Flip Flop Next State Maps

Flip flop Next state maps

v sequential network design16

Flip flop 1 (J1, K1)

Current

Next state Y1

Flip flop 1 (J1, K1)

X

(y1y0)

Current

Next state Y1

0

1

X

J1 K1

J1 K1

(y1y0)

0

1

0 0 00

0 1 01

1 0 01

1 1 dd

Next transition for X=0 and X=1

V. Sequential Network Design

Example 1: STEP 7

  • Flip Flop Excitation Maps
  • Determine transitions of flip flop
  • For each transition, give the input that cause the transition
  • (Depends on the type of flip flops)

Assume JK flip flop for y1 and y0

0 0 0 d 0 d

0 1 0 d 1 d

1 0 d 1 d 0

1 1 d d d d

v sequential network design17

Flip flop 0 (J0, K0)

Current

Next state Y0

Flip flop 0

X

(y1y0)

Current

Next state Y0

0

1

X

(y1y0)

J0 K0

J0 K0

0

1

00 10

01 10

10 10

11 dd

V. Sequential Network Design

Example 1: STEP 7

Flip Flop Excitation Maps

Assume JK flip flop for y1 and y0

0 0 1 d 0 d

0 1 d 0 d 1

1 0 1 d 0 d

1 1 d d d d

Next transition for X=0 and X=1

v sequential network design18

J1

y1y0

00

01

11

10

X

0

0 0 d d

Flip flop 1 (J1, K1)

1

0 1 d d

Current

Next state Y1

X

(y1y0)

J1 = x•y0

0

1

J1 K1

J1 K1

0 0 0 d 0 d

K1

0 1 0 d 1 d

y1y0

00

01

11

10

1 0 d 1 d 0

X

0

1 1 d d d d

d d d 1

1

d d d 0

K1 = x’

V. Sequential Network Design

Example 1: STEP 8

Flip Flop Excitation Equations (Input circuits of flip flops)

  • Derive K- Maps from excitation maps
  • Use K-maps to derive flip flop input equations

J1 input

K1 input

v sequential network design19

J0

y1y0

00

01

11

10

X

0

1 d d 1

Flip flop 0 (J0, K0)

1

0 d d 0

Current

Next state Y0

X

(y1y0)

J0 = X’

0

1

J0 input

J0 K0

J0 K0

0 0 1 d 0 d

K0

0 1 d 0 d 1

y1y0

00

01

11

10

1 0 1 d 0 d

X

0

1 1 d d d d

d 0 d d

1

d 1 d d

K0 input

K0 = X

V. Sequential Network Design

Example 1: STEP 8

Flip Flop Excitation Equations (Input circuits of flip flops)

  • Derive K- Maps from excitation maps
  • Use K-maps to derive flip flop input equations
v sequential network design20

Z

y1y0

00

01

11

10

X

0

0 0 d 1

1

0 1 d 1

Z = y1 + x•y0

K-map of output Z

V. Sequential Network Design

Example 1: STEP 9

Determine the output logic circuit

State/Output table (Mealy Machine)

NS

Output Z

y1y0

X=0

X= 1

X=0

X= 1

00 01 00

0 0

01 01 10

0 1

10 01 10

1 1

11 dd dd

d d

v sequential network design21

Input circuit

y1

J1

Q

Memory components

K1

J0

Q

y0

K0

Output circuit

CLK

Z

OR

V. Sequential Network Design

Example 1: STEP 10

Draw the circuit: (Flip flops and logic gates)

X

v sequential network design22
V. Sequential Network Design

Homework

  • Design the 01 sequence detector as a Moore machine. The ouput is reset
  • 0 when a 00 sequence is detected.
  • Design the detectector using:
  • clocked JK flip flops
  • clocked D flip flops
v sequential network design23

B,0

Overlapping

1

1

0

1

0

C,0

0

A,0

D,0

E,1

1

1

0

0

V. Sequential Network Design

Example 2

Give the state diagram of a clocked sequential circuit that recognizes the input

sequence 1010, including overlapping.

For example, for the input sequence

X = 00101001010101110, the corresponding output Z is

Z = 00000100001010000

State diagram (Moore Machine):

v sequential network design24
V. Sequential Network Design

Example 3

  • Design a Moore synchronous sequential circuit to detect a string of
  • of three or more consecutive 1’s in an arbitrary input string.
  • Design the detectector using:
  • clocked JK flip flops
  • clocked D flip flops
v sequential network design25
V. Sequential Network Design

Example 4

Using D flip flops, design a Moore synchronous sequential comparator circuit

to determine which of the two multi-bits binary numbers X and Y (of equal

Length) is larger. The comparison is carried out from left

(Most Significant Bit) to right. Both MSB are used as input to the circuit.

Assume two outputs Z1Z2 such that:

Z1 = 1 if X > Y

Z2 = 1 if X < Y

Z1= Z2 = 0 if X = Y

v sequential network design26
V. Sequential Network Design

Example 5

Design a two-bit clocked sequential counter circuit that counts clock pulses.

design examples
Design examples
  • Example1
  • Give the state diagram of a clocked sequential circuit that recognizes the input sequence 1010, including overlapping. For example, for the input sequence
  • X = 00101001010101110, the corresponding output Z is
  • Z = 00000100001010000
  • Example2
  • Design a Moore synchronous sequential circuit to detect a string of of three or more consecutive 1’s in an arbitrary input string. Design the detectector using:
  • clocked JK flip flops
  • clocked D flip flops
  • Example3
  • Using D flip flops, design a Moore synchronous sequential comparator circuit to determine which of the two multi-bits binary numbers X and Y (of equal Length) is larger. The comparison is carried out from left (Most Significant Bit) to right. Both MSB are used as input to the circuit.
  • Assume two outputs Z1Z2 such that:
  • Z1 = 1 if X > Y
  • Z2 = 1 if X < Y
  • Z1= Z2 = 0 if X = Y
  • Example4
  • Design a two-bit clocked sequential counter circuit that counts clock pulses.