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Introduction to High Momentum Trigger in PHENIX Muon Arms

Introduction to High Momentum Trigger in PHENIX Muon Arms. RIKEN/RBRC Itaru Nakagawa 中川格. RHIC Accelerator Complex. Polarized Proton-Proton Operation at RHIC. test. production. test. production. 2. Forward ( North&South ) Muon Arms. Muon Tracking Chambers

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Introduction to High Momentum Trigger in PHENIX Muon Arms

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  1. Introduction to High Momentum Trigger in PHENIX Muon Arms RIKEN/RBRC Itaru Nakagawa 中川格

  2. RHIC Accelerator Complex Polarized Proton-Proton Operation at RHIC test production test production 2

  3. Forward (North&South) Muon Arms

  4. Muon Tracking Chambers 3 stations of Cathode strip chambers Each station has multiple planes for redundancy Slow read out -> No trigger Muon Identifier 5 layers of Iarocci tubes in x and y 80 cm of steel plate absorber (total) Provides trigger p > 2 GeV Current Muon System B   MuID MuTr St#1 St#2 St#3 Same configuration in South 5

  5. 100 GeV Trigger Rate @ sqrt(s) = 200 GeV -Trigger Rate < 2 kHz

  6. 250 GeV Trigger Rate @ sqrt(s) = 500 GeV Design Luminosity √s = 500 GeVσ=60mb L = 1.5x1032/cm2/s Rejection Factor ~ 4500 Rate ~9MHz !! 

  7. High Momentum Muon Trigger New Trigger Upgrade Run11 500 GeV Projection σtot=60mb L=1.5x1032cm-2s-1 Rate 9 MHz BBCMuID Rejection Power RP~100 Trigger Upgrade RP ~ 45 90 kHz W RPtot ~ 4500 2 kHz PHENIX Band Width for Muon Required Rejection Power MuID Trigger High Rejection Power High Efficiency

  8. PHENIX Muon Trigger Upgrade • Three dedicated trigger RPC stations (CMS design): • R1(a,b): ~12mm inj, 4x θ pads • R2: ~5.4mm in j , 4x θ pads • R3: ~6.0mm in j, 4x θ pads • (Trigger only – offline segmentation higher) NSF (Funded) • MuTr front end electronics • Upgrade to allow LL1 information JSPS (Funded) R3 R1(a+b) r=3.40m MuTr Rejection ~12,000, beam background immune.

  9. Momentum Dependent Trigger How New Trigger Works? B PT Sensitive Trigger Does The Job • Search for a Stiff Track ONLINE! • Slow MuTr could trigger with INCOMING tracks • Fast RPC will reject them 10

  10. B W Trigger System Trigger events with straight track (e.g. Dstrip <= 1) ~10s Trigger MuTr FEE Interaction Region Rack Room

  11. B W Trigger System Trigger events with straight track (e.g. Dstrip <= 1) MuTRG Data Merge Amp/Discri. Transmit Trigger 5% Optical MuTRG MRG MuTRG ADTX 1.2Gbps Trigger 2 planes MuTr FEE 95% Interaction Region Rack Room

  12. Resistive Plate Counter (RPC) (Φ segmented) B W Trigger System Trigger events with straight track (e.g. Dstrip <= 1) RPC FEE MuTRG Data Merge Amp/Discri. Transmit Trigger 5% Optical MuTRG MRG MuTRG ADTX 1.2Gbps Trigger 2 planes RPC / MuTRG data are also recorded on disk. MuTr FEE 95% Interaction Region Rack Room

  13. Resistive Plate Counter (RPC) (Φ segmented) B W Trigger System Trigger events with straight track (e.g. Dstrip <= 1) Level 1 Trigger Board Trigger RPC FEE MuTRG Data Merge Amp/Discri. Transmit Trigger 5% Optical MuTRG MRG MuTRG ADTX 1.2Gbps Trigger 2 planes RPC / MuTRG data are also recorded on disk. MuTr FEE 95% Interaction Region Rack Room

  14. Resistive Plate Counter (RPC) (Φ segmented) B W Trigger System Trigger events with straight track (e.g. Dstrip <= 1) Level 1 Trigger Board Trigger RPC FEE MuTRG Data Merge Amp/Discri. Transmit Trigger 5% Optical MuTRG MRG MuTRG ADTX 1.2Gbps Trigger 2 planes RPC / MuTRG data are also recorded on disk. MuTr FEE 95% Interaction Region Rack Room

  15. Resistive Plate Counter (RPC) (Φ segmented) B W Trigger System (Final) Trigger events with straight track (e.g. Dstrip <= 1) Level 1 Trigger Board RPC FEE DCM DCM MuTRG Data Merge Amp/Discri. Transmit Trigger 5% Optical MuTRG MRG DCM MuTRG ADTX 1.2Gbps Trigger 2 planes RPC / MuTRG data are also recorded on disk. MuTr FEE 95% Interaction Region Rack Room

  16. MuTrig-FEE Developers Tsutomu Mibe Kazuya Aoki MRG Board & DCMIF YoshiFukao ADTX Board Katsuro Nakamura MuTRG MRG MuTRG ADTX Kohei Shoji Kenichi Karatsu

  17. 2008 North Arm Installation 2009 South Arm

  18. New MuTRIG-FEE in North Arm  Before Install 2008 Install

  19. MuTrig-FEE Parameters MuTR Non-Stereo Gaps St1 St2 St3 2 of 3 AND 3 of 3 AND No MuTRG-FEE

  20. Resistive Plate Chamber(RPC)

  21. Hadron Absorber

  22. How much neutron backgrounds? • How we can reduce these background effect? Neutron Absorber + RPC1 Recap clamp Kentaro Watanabe YoshimitsuImazu

  23. MuTR-FEE Trigger Performance

  24. MuTRG System Run09 performance Better efficiency is the trade off of weak rejection power • MuID Algorithm • Track Matching w/ MuID • Timing cut w/ RPC • Track Matching w/ RPC • Neutron Backgrounds • etc ..  28 MuTrg-FEE xMuID

  25. LL1 Efficiencies MuTr LL1 boards developed by U.Iowa ADTX Josh Perry’s Online Monitor LL1 GL1 Trigger MRG DCMIF DCM Identical hit information

  26. LL1 Trigger Emulator Online Plot LL1 efficiency Stability Monitored by Sanghwa Park (SNU)

  27. Summary • Forward Muon Trigger Upgrade hardware developments are nearly final stage. Thanks for many students / young researchers. • We continue to improve performance of existing detectors (hardware and software wise). • Physics Analysis (not only W), performance improvement, trigger operation, maintenance, etc… There are many things to do!

  28. Back up Slides

  29. New Trigger Upgrade Efficiency Turn on Curve Not firing by low momentum track! W black : offline emulator red : GL1 fired MuID Trigger

  30. MuTR-FEE SG1 Trigger After Long Shutdown Before Long Shutdown AND2 Surviving BBC rate 2MHz! Rejection Power OR PHENIX Band Width Limit for Muon Improved Rejection Power after Long Shutdown or OR->AND2 Logic?

  31. Summary • New Muon Trigger-FEE SG1 trigger is under operation as physics trigger for W • LL1 demonstrates stable performance w/ almost 100% efficiencies for both North&South • Trigger efficiency behaves pretty much as we designed. Low efficiency in low PT, high efficiency in high PT regions. • SG1xMUIDxBBC trigger functions with sufficient rejection power so far up to BBC rate ~ 2MHz. • Combined with RPC will provide even stronger and more reliable trigger for W.

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