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A Device-Controlled Dynamic Configuration Framework Supporting Heterogeneous Resource Management Heng Tan Ronald Demara
Proposed Work: Multilayer Runtime Reconfiguration Architecture (MRRA) • Develop MRRA fast reconfiguration paradigm for the CRR approach • Validate with real hardware platform along with detailed performance analysis • Serve as the first general-purpose framework for a wide variety of applications that require reconfiguration process during operation • Extend existing theories on reconfiguration
Loosely Coupled Solution The Virtex-II Pro is mounted on a development board which can then be interfaced with a WorkStation running Xilinx EDK and ISE. The entire system operates on a 32-bit basis
Future Theoretical Work • Communication overhead, throughput and overall speed-up analysis • Translation Complexity Analysis • The quantity of information that needs to be translated to generate the reconfiguration bitstream • Simplification from file level to bit level is expected • Storage Complexity Analysis • The memory space that is required for the run-time algorithms
Operational Characteristics • Task: A function synthesized to a digital circuit in the form of module that can be programmed and downloaded into the reconfigurable device. A task has a size and a shape. • TaskModularity: The smallest granularity that this architecture deals with is at task level. The size and shape generate the area requirement of the task in CLBs. • General-purpose application scenario:The architecture may carry out an arbitrary number of tasks. There are no predefined constraints on the tasks. The functions of the tasks are also unknown a-priori. • Runtime scenario: The architecture does not know in advance when and what tasks will arrive and what their properties will be. When a task is generated, the system processes it online at runtime.
Issues to Address • Partitioning: Selecting computational resources to initialize as component • Placement: Determining the target location of the component on the reconfigurable fabric of the device • Routing: Interfacing the component to its surrounding resources • Generation: Generating the bitstream of the component at the target location, and • Configuration: Writing the generated bitstream to the appropriate portions of the underlying reconfigurable infrastructure of the reconfigurable fabric
Reconfigurable Module Bus Macro Reconfigurable or Fixed Module OPB Addr decoder Slave attach MIR/ Reset IPIF User Logic Routing: Reconfiguration Module Template Intermodule Signal Reconfiguration module Template
(Top-Level Design) Design Entry HDL Entry/Synthesis Initial Budgeting (Top-level Design) Design Entry HDL Entry/Synthesis (Module) Active Module Implementation (Module) Mapping Placement Routing Final Assembly (Top-Level Design and Modules) Mapping Placement Routing Download to device Generation: Partial Reconfiguration Flow