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Dezső Sima

Dezső Sima

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Dezső Sima

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  1. Dezső Sima Evolution of Intel’s Basic Microarchitectures - 2 Vers. 3.2 October 2012

  2. 1.Introduction 2.Core 2 3.Penryn 4.Nehalem 7.Westmere-EX 5.Nehalem-EX 6.Westmere Contents

  3. 9.Sandy Bridge Extreme Edition 10.Ivy Bridge 11.Overview of the evolution 8.Sandy Bridge 11.Haswell Contents

  4. 8.1 Introduction 8.2Advanced Vector Extension (AVX) 8.3On-die ring interconnect bus 8.4 On-die integrated graphics unit 8.5Enhanced turbo boost technology 8. Sandy Bridge

  5. 8.1 Introduction (1) 8.1 Introduction • Sandy Bridge is Intel’s new microarchitecture using 32 nm line width. • First delivered in 1/2011

  6. 8.1 Introduction (2) Main functional units of Sandy Bridge[143] Part 4 256 KB L2 (9 clk) 256 KB L2 (9 clk) 256 KB L2 (9 clk) 256 KB L2 (9 clk) 256 KB L2 (9 clk) 256 KB L2 (9 clk) 256 KB L2 (9 clk) Hyperthreading AES Instr. VMX Unrestrict. 20 nm2 / Core 32K L1D (3 clk) AVX 256 bit 4 Operands @ 1.0 1.4 GHz (to L3 connected) (25 clk) PCIe 2.0 256 b/cycle Ring Architecture 25.6 GB/s DDR3-1600 32 nm process / ~225 nm2 die size / 85W TDP

  7. 8.1 Introduction (3) Key features and benefits of the Sandy Bridge linevs the 1. generation Nehalem line [61]

  8. 8.1 Introduction (4) Overview of the Sandy Bridge based processor lines Sandy Bridge-E Sandy Bridge Section 9) Mobiles Core i3-23xxM, 2C, 2/2011 Core i5-24xxM//25xxM, 2C, 2/2011 Core i7-26xxQM/27xxQM/28xxQM, 4C, 1/2011 Core i7 Extreme-29xxXM , 4C, Q1 2011 Desktops Desktops Core i7-3960X, 6C, HT, vPro??, 11/2011 Core i7-3930K, 6C, HT, vPro??, 11/2011 Core i3-21xx, 2C,no HT, no vPro, 2/2011 Core i5-23xx 4C+G, no HT no VPro, 1/2011 Core i5/24xx/25xx, 4C+G, no HT, vPro, 1/2011 Core i7-26xx, 4C+G, HT, vPro, 1/2011 Core i7-2700K, 4C+G, HT, no vPro, 10/2011 Servers UP-Servers E3 12xx, 4C, Sandy Bridge-H2, 4C, 3/2011 DP-Servers E5 2xxx, Sandy Bridge-EP, up to 8C, Q4/2011 MP-Servers E5 4xxx, Sandy Bridge-EX, up to 8C, Q1/2012 Based on [62]and [63]

  9. 8.2 Advanced Vector Extension (AVX) (1) 8.2 Advanced Vector Extension (AVX) Introduction of AVX Sandy Bridge Figure: Evolution of the SIMD processing width [18] BMA-ból

  10. 8.2 Advanced Vector Extension (AVX) (2) 8 MM registers (64-bit), aliased on the FP Stack registers 8 XMM registers (128-bit) 16 XMM registers (128-bit) Northwood (Pentium4) Norhwood Northwood (Pentium4) 16 YMM registers (256-bit) Ivy Bridge Figure: Intel’s x86 ISA extensions - the SIMD register space (based on [18]) BMA

  11. 8.3 On-die ring interconnect bus (1) 8.4 The on die ring interconnect bus of Sandy Bridge[66] Six bus agents. The four cores and the L3 slices share interfaces.

  12. 8.4 On-die integrated graphics unit (1) Part4 8.5 Sandy Bridge’s integrated graphics unit[102] 12 EUs

  13. 8.4 On-die integrated graphics unit (2) Specification data of the HD 2000 and HD 3000 graphics [125] Part 4 -

  14. 8.4 On-die integrated graphics unit (3) Performance comparison: gaming[126] part 4 HD5570 400 ALUs i5/i7 2xxx/3xxx: Sandy Bridge i5 6xx Arrandale frames per sec

  15. 8.5 Enhanced turbo boost technology (1) 8.5 Enhanced turbo boost technology[64] Innovative concept of the 2.0 generation Turbo Boost technology The concept utilizes the real temperature response of processors to power changes in order to increase the extent of overclocking [64] Thermal capacitance Cooler

  16. 8.5 Enhanced turbo boost technology (2) Concept: Use thermal energy budget accumulated during idle periods to push the core beyond the TDP for short periods of time (e.g. for 20 sec). Multiple algorithms manage in parallel current, power and die temperature. [64]

  17. 8.5 Enhanced turbo boost technology (3) Intelligent power sharing between the cores and the integrated graphics[64]

  18. 8.5 Enhanced turbo boost technology (4) Intelligent power sharing between the cores and the integrated graphics[68]

  19. 8.5 Enhanced turbo boost technology (5) NHM/M WSM/M NHM/D WSM/D [61]

  20. 8.5 Enhanced turbo boost technology (6) Remark • Individual cores may run at different frequencies but all cores share the same power plane. • Individual cores may be shut down if idle by power gates.

  21. 9. The Sandy Bridge-E line

  22. 9. The Sandy Bridge-E line (1) 9 The Sandy Bridge-E line of processors (2. gen. Core i7 processors) Introduced in 11/2011 as a “precursor” of the upcoming DP/MP server lines. Key features vs the original Sandy Bridge line (1) a) 6 cores with 2 cores disabled but does not incorporate graphics [76].

  23. 9. The Sandy Bridge-E line (2) Sandy Bridge E Sandy Bridge (2x) 435 mm2 2.27 B trs 15 MB L3 216 mm2 995 mtrs 8 MB L2 [76] [61]

  24. 9. The Sandy Bridge-E line (3) Comparison of die parameters of recent DT processors [77]

  25. 9. The Sandy Bridge-E line (4) Cache/memory latencies of recent DT processors [77]

  26. 9. The Sandy Bridge-E line (5) b) 4 parallel memory channels (inherited from the server side) instead of 2 of the previous lines. Support of DDR3 of up to 1600 MT/s. A single DDR3-1600 DIMM per channel or 2 DDR3-1333 DIMMs per channel [78].

  27. 9. The Sandy Bridge-E line (6) c) 40 PCIe 2. gen. lanes to connect graphics cards directly to the processor instead of 16 to 32 of the previous generation Sandy Bridge [78]. d) LGA-2011 socketinstead of the LGA-1155 used in the pervious generation Sandy Bridge due to the increased number of memory channels connected to the processor..

  28. 9. The Sandy Bridge-E line (7) Main features of the Sandy Bridge-E line vs the Sandy Bridge line [77]

  29. 9. The Sandy Bridge-E line (8) Intel’s DT board for Sandy Bridge-E processors [79] (The DX79SI ATX board for the Core i7-3960X /3930K) Max. memory: 8 x 8 GB

  30. 10. The Ivy Bridge line

  31. 10. Te Ivy Bridge line – 10.1 Introduction (1) Merom1 NEW Microarchitecture 65nm Penryn NEW Process 45nm Nehalem NEW Microarchitecture 45nm Westmere NEW Process 32nm Sandy Bridge NEW Microarchitecture 32nm Ivy Bridge NEW Process 22nm Haswell NEW Microarchitecture 22nm TOCK TICK TOCK TICK TOCK TICK TOCK 10.The Ivy Bridge line 11.1 Introduction The Ivy Bridge is termed also as the 3. gen. Intel Core processors. Introduced: 4/2013 Tick-TockDevelopmentModel Figure 10.1: Intel’s Tick-Tock development model [Based on 1]

  32. 10.1 Introduction (2) Sandy Bridge 32 nm 216 mm2 995 mtrs 22 nm 160 mm2 1480 mtrs Ivy Bridge (Resized to 32 nm feature size) Figure 10.2: Contrasting the Sandy Bridge and Ivy Bridge dies [81]

  33. 10.1 Introduction (3) [84]

  34. 10.1 Introduction (4) Major innovations of Ivy Bridge [80]

  35. 11.2 The new 22 nm tri-gate process technology (1) 11.2 The new 22 nm tri-gate process technology [82]

  36. 10.2 The new 22 nm tri-gate process technology (1) [82]

  37. 10.2 The new 22 nm tri-gate process technology (1) [82]

  38. 10.2 The new 22 nm tri-gate process technology (1) [82]

  39. 10.2 The new 22 nm tri-gate process technology (1) [82]

  40. 10.2 The new 22 nm tri-gate process technology (1) Figure: Contrasting 32 nm planar and 22 nm tri-gate transistors [82]

  41. 10.2 The new 22 nm tri-gate process technology (1) [82]

  42. 10.2 The new 22 nm tri-gate process technology (1) [82]

  43. 10.2 The new 22 nm tri-gate process technology (1) [82]

  44. 10.2 The new 22 nm tri-gate process technology (1) Figure: Ivy Bridge chips on a 300 mm wafer

  45. 10.2 The new 22 nm tri-gate process technology (1) Table: Main implementation parameters of recent processors [81]

  46. 10.3 Supervisory Mode Execution Protection (SMEP) [83]

  47. 10.4 System architecture (1) [81]

  48. 10.4 System architecture (2) [81]

  49. 10.5 Performance (1) [81]

  50. 10.5 Performance (2) [81]