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TOPIC : Memory modeling. Module 4.1 : Memory modeling in Verilog. Memories. In digital simulation, one often needs to model register files, RAMs, and ROMs. Memories are modeled in Verilog simply as an array of registers.
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TOPIC : Memory modeling Module 4.1 : Memory modeling in Verilog
Memories • In digital simulation, one often needs to model register files, RAMs, and ROMs. Memories are modeled in Verilog simply as an array of registers. • Each element of the array is known as a word. Each word can be one or more bits. It is important to differentiate between n 1-bit registers and one n-bit register. • A particular word in memory is obtained by using the address as a memory array subscript.
Memory • Different types and sizes of memory, register file, stack, etc., can be formed by extending the vector concept. Thus the decleration Reg [15:0] memory[511:0]; • Declared an array called memory; it has 512 locations. Each location is 16 bits wide. The value of any chosen location can be assigned to a selected register or vice-versa; this constitutes memory reading or writing. The index used to refer a memory location can be a number or an algebraic expression which reduces to an integral value – positive, zero, or negative. • B = mem //data stored at mem is assigned to B
Memory decleration • Reg mem1bit[0:1023] //Memory mem1bit 1k 1-bit words. • Reg [7:0] membyte[0:1023]; //Memory membyte with 1k 8-bit words (bytes) • Membyte  //Fetches 1 byte word address is 511.
Initialization Memory from file • Verilog provides a very useful system task to initialize memories from a data file. Two tasks are provided to read numbers in binary or hexadecimal format. Keywords $readmemb and $readmemh are used to initialize memories : • Usage: • $readmemb(“<file_name>”, <memory_name>); • $readmemb(“<file_name>”,<memory_name>,<start_addr>,<finish_addr>); • NOTE : <start_addr>,<finish_addr> are optional.