Basic Input/Output Operations in VHDL

1. Digital Systems Design 2 VHDL: Basic Input/Output Ref. “VHDL Starter’s Guide”, Sudhakar Yalamanchili, Prentice Hall, 1998

2. Basic Input/Output • Thus far, presented examples of VHDL programs manipulate three classes of objects: • Variables, • Signals, and • Constants. • Based on the object and its type the following attributes will be determined: • Range of values that object can take, and • Operations that can be performed. • In analogous fashion a special class of objects that manipulate input/output functions exists in VHDL. • Manipulation of input/output functions necessitates the introduction of file type that permits declaration of file objects. • Files are special and serve as the interface between the VHDL programs and the host environment. Veton Këpuska

3. Basic Input/Output • Since files are manipulated in a very different manner from variables or signals, they deserved a special and distinct object type. • There are special operations that are performed only on files: • Reading (from file), • Writing (into file). • One of the most important application of file I/O in VHDL is the construction of testbenches. • A testbench is a VHDL program that is used to test VHDL models. Veton Këpuska

4. Basic Input/Output Operations • As with other objects (variable, signal, constant), the file object must have a name and be declared of corresponding type: type TEXT is file of string; • Declaration of a file type which can store ASCII data. • Library package TEXTIO provides procedures and functions for read/write –ing files of type TEXT. This package is placed in the library STD which is implicitly visible. However, use clause must specify this package if those functions are used. Veton Këpuska

5. Basic Input/Output Operations • From within a VHDL program we need some way to reference a file. This is performed via a file declaration: file infile : text open read_mode is “inputdata.txt”; file outfile : text open write_mode is “outputdata.txt”; • In order to read and write the files corresponding I/O procedures are needed. Standard VHDL procedures made available by the definition of the language are: • procedure READ (file f: TEXT; value: out type); • procedure WRITE (file f: TEXT; value: in type); • function ENDFILE (file f: TEXT) return boolean; Veton Këpuska

6. Basic Input/Output Operations • The above I/O procedures are implicitly declared following a file type declaration. • For details of specific procedures for reading and writing various data types refer to the development environment. • In addition to file READ, WRITE and ENDFILE procedures two functions are also provided that are implicitly declared following the file declaration: procedure FILE_OPEN (file f: TEXT; External_Name : in STRING; Open_Kind : in FILE_OPEN_KIND := READ_MODE); procedure FILE_CLOSE (file f: TEXT); Veton Këpuska

7. Basic Input/Output Operations • Let us assume that we have only the predefined file type of TEXT that contain only character strings. However, suppose that we wish to read and write binary signal values of the type std_logic_vector. • The following example illustrates how we can develop input/output procedures to read and write binary signal values based on available elementary character I/O operations that are provided by VHDL. • These new procedures can then be provided in a package to be used for general I/O. • This is practically the case with most VHDL development environments – set of functions in TEXTIO package is provided to read/write various data types. Veton Këpuska

8. library IEEE; use IEEE.std_logic_1164.all; use STD.textio.all; package classio is procedure read_v1d (variable f: in text; v: out std_logic_vector); procedure write_v1d (variable f: out text; v: in std_logic_vector); end; package body classio is procedure read_v1d (variable f: in text; v: out std_logic_vector) is variable buf: line; variable c: character; begin readline(f,buf); -- defined in TEXTIO for i in v’range loop read(buf,c); case c is when ‘X’ => v(i) := ‘X’; when ‘U’ => v(i) := ‘U’; when ‘Z’ => v(i) := ‘Z’; when ‘0’ => v(i) := ‘0’; when ‘1’ => v(i) := ‘1’; when ‘-’ => v(i) := ‘-’; when ‘W’ => v(i) := ‘W’; when ‘L’ => v(i) := ‘L’; when ‘H’ => v(i) := ‘H’; when others => v(i) := ‘0’; end case; end loop end; procedure write_v1d (variable f: out text; v: in std_logic_vector) is variable buf: line; variable c: character; begin for i in v’range loop case v(i) is when ‘X’ => write(buf,‘X’); when ‘U’ => write(buf,‘U’); when ‘Z’ => write(buf,‘Z’); when ‘0’ => write(buf, character’(‘0’)); when ‘1’ => write(buf,character’(‘1’)); when ‘-’ => write(buf,‘-’); when ‘W’ => write(buf,‘W’); when ‘L’ => write(buf,‘L’; when ‘H’ => write(buf,‘H’; when others => write(buf, character’(‘0’)); end case; end loop writeline(f,buf); end; end classio; An Example of Using Character I/O Veton Këpuska

9. Using the Classio Package • An example of how the procedures and the package presented in previous example how might be used is illustrated in the next example. • This example reads 16-bit vetors from infile.txt and writes them out the file outfile.txt. • Note that by changing the resolution of the variable check to 32 bits, the same procedure can be used for reading and writing 32-bit vectors. Veton Këpuska

10. library IEEE; use IEEE.std_logic_1164.all; use STD.textio.all; use WORK.classio.all; entity checking is end checking; architecture checking_behavioral of checking is begin process -- -- declare pointers to the input and output files -- file infile : TEXT open read_mode is “infile.txt”; file outfile : TEXT open write_mode is “outfile.txt”; variable check : std_logic_vector(15 downto 0) := to_stdlogicvector(x”0008”); begin -- -- copy the input file contents to the output file -- wait for 10 ns; while not (endfile(infile)) loop read_v1d(infile, check); write_v1d(outfile, check); end loop; end process; end checking_behavioral; Example of the use of the package classio.vhd Veton Këpuska

11. The Package TEXTIO • The package TEXTIO is a standard package supported by all VHDL simulators. This package provides a standard set of: • files types, • data types, and • input/output functions. • For example: • text object type, and • File handles for std_input and std_output. • read() and write() procedures are overloaded to handle various data types. Veton Këpuska

12. Testbenches in VHDL • Much of the motivation for simulation is to be able to test designs prior to construction and use of the circuit. • How would one test and electronic component? • Intuitively one would provide a set of inputs and check the observed output values against the corresponding correct set/expected set of output values. • When developing VHDL models, one would face the similar situation. • How can a model be tested to ensure: • The model is operating as intended/designed, and • The design is correct? • Verifying a design via simulation is certainly more cost-effective than testing a fabricated part and then determining that it has a design error that must be fixed. • Most simulators provide commands to apply stimulus to the input ports of a design entity. • By tracing and viewing the resulting values of the signals on the output ports, it can be determined whether the model is operating correctly. • The outlined test frame is itself a digital system and one should be able to describe the operation of the tester in VHDL. Veton Këpuska

13. Testbenches in VHDL • The logical behavior of the tester is simple: • The tester model generates sequences of inputs, • The outputs of the module being tested are read, • This response is compared to ideal/expected behaviour. • This behavior is captured in the notion of a testbench and is illustrated in following figure. output port Testbench Model under Test Tester tester.vhd model.vhd testbench.vhd input port Veton Këpuska

14. Writing a Testbench • Need to write a testbench to test the VHDL model of the positive edge triggered D flip-flop developed earlier (VHDL model is presented in the next slide for convenience). It is thus required to generate a clock signal and a sequence of values on the D input signals. We must also test the Set (S) and Reset (R) operations. A sample of clock and D test signal patterns are depicted in the figure as well as output waveform. Veton Këpuska

15. library IEEE; use IEEE.std_logic_1164.all; entity asynch_dff is port (R,S,D,Clk: in std_logic; Q,Qbar: out std_logic end asynch_dff; architecture asynch_dff_func of asynch_dff is begin Dff_process: process (R,S,Clk) begin if (R = ‘1’) then Q <= ‘0’ after 5 ns; Qbar <= ‘1’ after 5 ns; elsif (S = ‘1’) then Q <= ‘1’ after 5 ns; Qbar <= ‘0’ after 5 ns; elsif (Clk’eventand Clk=‘1’) then Q <= D after 5 ns; Qbar <= (not D) after 5 ns; endif; end process Dff_process; end asynch_dff_func; Positive Edge D Flip-Flop with Asynchronous Set and Reset inputs Veton Këpuska

16. Description of the Tester Module. • An example of a tester module that generates the clock signal and applies a set of test vectors to the D flip-flop model is shown in the next slide. • The process named clk_process generates a clock signal with a period of 20 ns. This process ececutes concurrently with the io_process. • The io_process reads test vectors from file infile.txt. Each test vector is 5 bits long. The first 3 bits correspond to R,S, and D. The last two bits are the corresponding correct values of Q and Qbar. Collectively these five values constitute one test vector. • The input test vector values are applied to the flip-flop model at 20 ns intervals at the rising edge of the clock. From the timing diagram one would be able to generate test vectors included in file infile.txt: • 11001 • 01101 • 11110 • 10010 • 10011 -- illegal case Veton Këpuska

17. library IEEE; use IEEE.std_logic_1164.all; use STD.textio.all; use WORK.classio.all; -- -- this is the module generating the tests -- entity srtester is port(R,S,D,Clk: out std_logic; Q,Qbar: in std_logic); end srtester; architecture behavioral of srtester is begin clk_process: process begin Clk <= ‘1’, ‘0’ after 10 ns, ‘1’ after 20 ns, ‘0’ after 30 ns; wait for 40 ns; end process clk_process; io_process: process file infile: TEXT open read_mode is “infile.txt”; file outfile: TEXT open write_mode is “outfile.txt”; variable buf: line; variable msg: string(1 to 19) := “This vector failed!”; variable check: std_logic_vector(4 downto 0); begin while not (endfile(infile)) loop read_v1d(infile, check); R <= check(4); S <= check(3); D <= check(2); wait for 20 ns; if ((Q /= check(1)) or (Qbar /= check(0))) then write(buf,msg); writeline(outfile, buf); write_v1d(outfile, check); endif; end loop; wait; -- this wait statement is important to allow the simulation to halt! end process io_process; end behavioral; Behavioral Description of the Tester Module. Veton Këpuska

18. library IEEE; use IEEE.std_logic_1164.all; use STD.textio.all; entity srbench is end srbench; architecture structural of srbench is component asynch_dff port(R,S,D,Clk: in std_logic; Q,Qbar: out std_logic); end component; component srtester port(R,S,D,Clk: out std_logic; Q,Qbar: in std_logic); end component; -- -- configuration specification -- for T1: srtester use entity WORK.srtester(behavioral); for M1: asynch_dff use entity WORK.asynch_dff(behavioral); signal s_r,s_s,s_d,s_q,s_qb,s_clk: std_logic; begin T1: srtester port map (R=>s_r,S=>s_s,D=>s_d,Q=>s_q,Qbar=>s_qb, Clk=>s_clk); M1:asynch_dff port map (R=>s_r,S=>s_s,D=>s_d,Q=>s_q,Qbar=>s_qb, Clk=>s_clk); end structural; Structural Description of the Tester Module. Veton Këpuska

19. Veton Këpuska