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C. Jiao, Y. Zheng, A. Modic , T . –I. Smith, A. C. Ahyi and S. Dhar

4H-SiC MOSFETs with: ( i ) Phosphosilicate glass gate dielectric (ii) Surface counter-doping with Sb. 10 th ARL SiC MOS Workshop, College Park, MD, Aug 13, 2015. C. Jiao, Y. Zheng, A. Modic , T . –I. Smith, A. C. Ahyi and S. Dhar Dept. of Physics, Auburn University, Auburn, AL, USA.

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C. Jiao, Y. Zheng, A. Modic , T . –I. Smith, A. C. Ahyi and S. Dhar

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  1. 4H-SiC MOSFETs with: (i) Phosphosilicate glass gate dielectric (ii) Surface counter-doping with Sb 10th ARL SiC MOS Workshop, College Park, MD, Aug 13, 2015 C. Jiao, Y. Zheng, A. Modic, T. –I. Smith, A. C. Ahyi and S. Dhar Dept. of Physics, Auburn University, Auburn, AL, USA

  2. Channel mobility problem in SiC power MOSFETs J. W. Palmouret al., ISPSD 2014 • Channel mobility in commercial MOSFETs low ~20 cm2 V-1 s-1 • Channel can contribute up to 50% of total on-resistance • Higher mobility Smaller chip size, lower operating oxide fields, less design constraints, lower blocking voltages etc.

  3. SiO2-4H-SiC interface traps Schorner et al IEEE EDL, 20, 241 (1999) Oxide Nano-scale imperfections and defects at/near the SiO2/SiC interface current SiC J = .E = q.n.µ.E • Interface traps reduce both nand  by trapping and Coulomb scattering (as-oxidized, without passivation) 4H-SiC 3

  4. Interface trap passivation As-oxidized NO annealed E. Arnold et al. IEEE Trans. Elec. Dev (2001) S. Dhar et al. Jn. Appl. Physics (2010) 1175C NO annealing, tox= 550 A Ideal model Slope=Cox/q Ideal model Slope=Cox/q Electron density (1012 cm-2) Cox= SiO2 capacitance Measured slope≈Cox/q Measured Slope<<Cox/q Gate Voltage (V) • NO: Reduction of trap density: >1013 cm-2 ~1012 cm-2 • As-ox: >90% free e- remain trapped 4

  5. Si MOSFET: ‘Universal’ mobility behavior 1/ch= 1/phonon + 1/coulomb +1/SR Takagi et al.,IEEE TED, 12, 2357 (1994) • Low electron density n: Coulomb scattering • Moderate n, moderate temperature: Phonon scattering • High n: Surface roughness scattering

  6. Mobility in NO annealed 4H-SiC MOSFET Regime 2 Regime 1 S. Dhar et al., ICSCRM (2011) • T< 373 K, T µ • Coulomb scattering • Thermally activated transport • T >400 K, T µ  • Coulomb scattering at low fields • Phonon and surface roughness scattering at high E fields n increasing 1175C NO tox= 550 A No n dependence T1

  7. Summary of 4H-SiC MOS interface treatments • Group I : • Hydrogen/wet anneals: μ> 200 cm2 V-1s-1Si-face, weakly bonded, instability • Na, K: μ~ 200 cm2 V-1s-1 , heavy instability • (mid 2000s, Chalmers Univ., Sweden) • Cs, Rb: μ~ 40 cm2 V-1s-1 , high Dit, • Lichtenwalner et al., ApplPhysLett.(2014) • Group II: Alkaline earth metals • Ca, Ba, Sr (oxide interlayers): μ~ 90 cm2 V-1s-1 , low Dit, • Lichtenwalner et al., ApplPhysLett. (2014) • Group III: • B (Borosilicate glass): μ~ 100 cm2 V-1s-1 , low Dit, • Okamoto et al., IEEE EDL, (2014) • Group V: • N (Various processes): μ~ 35cm2 V-1s-1 , low Dit, most reliable oxide • Most widely studied SiC MOS system 2000-2014 • P (Phosphoslicate glass): μ~ 100 cm2 V-1s-1 , low Dit, poor long term stability Okamoto et al., IEEE EDL, (2010) • Sb (surface doping) + N: μ~ 100 cm2 V-1s-1 , low Dit, technologicallypromising • Modic et al., IEEE EDL, (2014) THIS TALK

  8. Scaling between interface trap density and mobility Phospho-silicate glass (PSG) 1/ch= 1/phonon + 1/coulomb +1/SR ‘Thin PSG’ • NO annealing: Most established trap passivation method •  scales with number of interface traps (Rozenet al. IEEE TED, 2011) • Trapping and Coulomb scattering limited at low gate voltages N3 =Standard NO NO + H N4 N2 N1 N0

  9. Recent Results: Non-scaling between trapping and mobility 1/ch= 1/phonon + 1/coulomb + 1/SR PSG (a-face) • Surface counter doping by N and P • Inaccurate Dit measurements as ‘fast traps’ not included. (Yoshioka et al. , J. Appl. Phys., 2012) NO (a-face) PSG process A N plasma (Si-face)

  10. Surface counter-doping Fiorenza et al. APL, 103, 153508 (2013) • Nitridation and phosphorus treatments lead to unintentional surface counter-doping

  11. ‘Fast states’ and the C-ψsmethod

  12. What is PSG? SiO2 + P2O5 (P2O5)x(SiO2)1-x SiO2 PSG SiC SiC • Advantages and disadvantages: • Low Dit • High • Instability • Polarization at low E-field stress • Electron/hole trapping at high E-field stress

  13. Phosphosilicate glass (PSG) formation process 900~1100°C 4POCl3 + 3O2 2P2O5 + 6Cl2 Condition: Maintain POCl3 at15°C; bubble through by N2; Anneal at 900~1100°C (15min) flowing O2; Post anneal (drive-in, 30min) with N2 at same temperature as annealing. Allows the study of annealing temperature variation

  14. Phosphorus uptake with temperature variation Courtesy: C. Xu and L.C. Feldman, Rutgers Univ.

  15. Reason for different P uptake (P2O5)x(SiO2)1-x During the drive-in annealing, some P2O5 is lost to the gas phase by evaporation. Reference: P. Balk and J.M. Eldridge, “Phosphosilicate Glass Stabilization of FET devices”, IEEE, 1969

  16. Interface traps correlation with P coverage C-ψscharacterization Taking ‘fast states’ into account, higher P coverage leads to lower Dit Courtesy: C-ψs code provided by D. Morisette, Purdue Univ.

  17. PSG: Lower density of ‘fast traps’ Low temperature G-ω measurement Wei-ChiehKao et al., Semiconductor Science and Tech., 2015 PSG NO 100K 100K

  18. PSG Instability BTS condition: 150°C, +1.5MV/cm, 5 min

  19. Two competing mechanisms of instability: • trapping and polarization • BTS: qNnet = q(Ntrp - Npol) = Cox × ∆VFB(1) • Relaxation (20 days): Npol≈ 0 , qNtrp = Cox × ∆VFB(2) • (assumption: electron trapping relaxes much slower than polarization) Devices with 1 h BTS: P Polarization scales with phosphorus uptake.

  20. Field-effect mobility dependence on P Ni At high E-field, mobility of 1000°C PSG is highest. Possible reason: Trade-off between trap passivation and counter-doping Mo Gate Ni PSG N+ N+ L = 150μm, W = 290μm P-type SiC

  21. Temperature dependence of mobility: PSG : T ↑, ↑ : T ↑, ↓ 900 oC PSG : weak T dependence 1100 oC PSG

  22. PSG Summary • POCl3 annealing temperature variation causes different P interface coverage • Correlation: higher P coverage results in lower Dit • Two competing mechanisms of instability identified: trapping and polarization.Polarization charge scales with P uptake. • Correlation between P coverage and needs further investigation • Temperature dependence of shows different limiting mechanisms: Coulomb scattering andsurface roughness scattering .

  23. Separation of trap passivation and counter-doping effects • Difficult to investigate using N or P as they result in both effects • Heavier dopants (As, Sb) not expected to chemically passivate dangling bonds • Surface counter-doping with Sb

  24. Effects of surface counter-doping ~1-3 nm doped n-type Metal Dielectric p-type Semiconductor • Higher carrier density at same E • Less traps filled at VT due to less band-bending, efficient screening (C ) • E  SRfor same carrier density • Ideally VT reduction is smaller as counter-doping thickness is reduced • In practice, VT determined by combination of doping and interface charge

  25. Sb surface doping process SIMS

  26. Sb profile after oxidation • ~75% of Sb lost during oxidation • Total interfacial amount : ~5.7E12 cm-2 • Total activated amount:~10% • Width of profile limited by depth resolution of SIMS. Layer < 10 nm • No crystal damage detected by ion scattering SiC SiO2 FWHM ~10 nm

  27. Surface counter-doping results p-well: 6E15 cm-3 Sb+NO T=300 K

  28. Sb acts as a dopant but does not passivate traps ‘Sb + NO’ ‘Sb only’ Low temperature High temperature Ec Ec EF EF EF - V V - n type EF - - n type - - - - Ei Ei Ev Ev

  29. Temperature dependence of ‘Sb+NO’ mobility Phonon scattering surface roughness Trap limited • Low field performance at high temperature better than NO • High field performance at higher temperature similar to NO • Low temperature behavior same as NO

  30. ‘Universal’ mobility behavior for NO annealed interfaces Coulomb screening limited FE mobility (cm2 V-1 s-1) surface roughness

  31. ‘Sb+NO’: Threshold voltage stability

  32. Sb process applied to heavier doped p-wells: Sb Al

  33. Sb process applied to heavier doped p-wells: P-well: 1E17 cm-3, tox: ~60 nm Main advantage of surfacecounter-doping : Higher sub-threshold slope

  34. Sb process applied to heavier doped p-wells: P-well: 5 E17 cm-3, tox: ~60 nm • Higher S can be obtained on heavy p-wells • Process optimization: Uneven activation/loss of Sb

  35. Summary • Highlights of recent SiC MOS channel engineering results presented • Transport limited by ‘fast traps’ and ‘surface roughness’ • Details of these mechanisms not clear • ‘Universal’ mobility behavior in SiC MOSFETs identified • PSG is a unique model system to study channel transport with minimal effects of trapping • Surface counter-doping processes have strong potential for threshold voltage control and sub-threshold slope improvement in practical MOSFETs

  36. Acknowledgements • A. C. Ahyi, T.-Isaacs Smith, A. Modic, C. Jiao, Y. Zheng (Auburn group) • G. Liu and L. C. Feldman (Rutgers University) • D. Morissette and J.A. Cooper (Purdue University) • S.T. Pantelides and group (Vanderbilt University) • P. Mooney (Simon Fraser University) • M. Goryll (Arizona State) • R. Kaplar (Sandia) • A. Lelis (ARL)

  37. THANK YOU !!

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