DFT Technologies for High-Quality Low-Cost Manufacturing Tests

1. DFT Technologies for High-Quality Low-Cost Manufacturing Tests Yuval Snir JTAG 2006

2. Agenda • Background – Two major fault models • Problem – Exploiting a given tester memory • Main goal – Two effective implementation solutions

3. Background • The Shrinkage of semiconductor devices brought a new distribution of defects • Timing defects have become more significant (at least 2% of all defects)

4. Background • For 130 nm fabrication • Of yield 70% • No statistical faults • Defect rate will be 0.7% 7000 defective devices un detected per million (DPM)

5. Fault Models s@0 -b s@1-b true • Stuck-at fault-model: • the most popular fault model used in practice • a line whose status is stuck at a given value (normally 0 or 1).

6. fault Models • At-speed fault model: • Example: Initialization B=1 Opposite value Propagates from B to C capture launch

7. The Problem • Desired fast & low cost technologies tests • Transition pattern set is 3-5 bigger then stuck-at pattern set • Sometimes there isn’t enough room on the tester memory for both pattern sets. • Yields expensive tester reloads of the memory.

8. solutions 1. Effective Merging At-Speed with Stuck-At Patterns 2. EDT – Embedded Deterministic Test

9. The TDF (Transition delay fault) patterns also detect a significant percentage of stuck-at faults Truncate TDF patterns Merging At-Speed with Stuck-At Patterns Sets

10. Merging Patterns – Example Design Design demands: Characteristic of the design • The tester can hold up to 10,000 test pattern • The highest priority – best possible coverage for stack@ • One TDF pattern set for each clock domain and one For cross clock domain.

11. Merging Patterns Test generation results before optimization • Due to the typically slow operation of the tester The TDF test coverage is only 85.14%.

12. Merging Patterns Test generation results before truncation & optimization

13. Merging Patterns • Flow for generating higher coverage: • Arrange TDF test patterns from most significant to least • Truncate TDF patterns ( 90% of the overall achievable) • Fault grade the truncated TDF patterns for SAF • Generate top-off SAF pattern set

14. Merging Patterns Test generation results after truncation & optimization

15. Merging Patterns Test generation methodology comparison

16. EDT-Embedded deterministic test Two additional blocks to the traditional ATPG: • Decompressor • Compactor

17. EDT-Embedded deterministic test • The blocks are in the scan chain path • System core isn’t affected • Immunity for logic changes • Tester see the original design

18. EDT-Embedded deterministic test • The decompressor: • Only 1% - 5% of scan cells get specified • EDT – compression is done prior to random fill • Shorter Chains - fewer cycles and data • Less costly tester can be used Attributes: Extremely high encoding capacity, low silicon area And high speed of operation

19. EDT-Embedded deterministic test • The compactor: • Ability to handle any number of X values • Support for production diagnostics directly from the compressed patterns

20. EDT-Embedded deterministic test • example: • Same coverage • Effective reduction of 100X in data volume and test time • One ATPG scan pattern occupies 11292 vectors One EDT scan pattern occupies 80 vectors only!

21. I have to go now