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Status – Week 206

Status – Week 206. Victor Moya. Summary. Fetch Cache. ColorCache. ColorWrite. Next week. Fetch Cache. Interface: Fetch. Reserves a cache line and requests the data to memory. Writes the line data to memory if there was modified data. Allocate. Reserves a line.

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Status – Week 206

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  1. Status – Week 206 Victor Moya

  2. Summary • Fetch Cache. • ColorCache. • ColorWrite. • Next week.

  3. Fetch Cache • Interface: • Fetch. • Reserves a cache line and requests the data to memory. • Writes the line data to memory if there was modified data. • Allocate. • Reserves a line. • Writes the line data to memory if there was modified data. • Sets write mask mode (for memory transactions).

  4. Fetch Cache • Interface: • Read • Reads an amount of data from a fetched line. • Write • Writes an amount of data to a fetched/allocated line. • Unreserves the line. • Write Masked. • Writes using a write mask an amount of data to a fetched/allocated line. • Unreserves the line. • Unreserve: • Unreserves a line (when no write is performed after fetch/allocate).

  5. Fetch Cache • Interface: • Flush: • Flush mode. • Adds modified lines to the memory request queue. • To be called once per cycle when flushing the cache. • ProcessMemoryTransaction: • Receives and processes memory transactions (MT_READ_DATA). • Is called only when there are new transactions. • Update: • Generates new memory transactions. • Updates fetch cache timing (buses, ports) and memory request queue. • To be called ocne per cycle.

  6. Fetch Cache • Suggested modifications: • Flush: • Just sets a flag => flushMode. • The flush tasks are done at update. • Update: • Rename to clock (as that is what is …). • Add another function to retrieve the generated memory transactions rather than using update/clock to return them.

  7. Fetch Cache • Problems: • Memory bus width vs Cache port width. • portWidth < memBusWidth makes sense? • Add buffers to reduce contention. • Mixed write and write masked calls are not supported. • Write uses ‘fast’ 4 byte copy. • Write mask uses slow 1 byte copy and set mask.

  8. Fetch Cache • Problems: • Makes sense to have timing at fetch cache will not being a Box?

  9. ColorCache • Not a box (yet). • Now is just a wrapper for Fetch Cache: • Just hides size parameter of the read/write operations.

  10. ColorCache • To be added: • Fast clear. • State block memory marks color blocks/lines as cleared (or compressed/uncompressed). • Intercepts memory transactions for cleared lines. • Color compression. • Intercepts memory transactions. • Compress (write) or decompress (read) color data. • Write only mode (write buffer, masked memory transactions): • Requires read of uncompressed lines/blocks before recompression/write.

  11. ColorCache • Implement as a box: • Current interface is converted to signals: • Command Signal: • Flush/Reset. • Allocation Signal: • Fetch/Allocate/Unreserve. • Write Signal: • Write/Write Masked. • Read Signal: • Read. • Memory Input Signal: • ProcessMemoryTransaction • MemoryOutputSignal: • Update.

  12. ColorCache • Implement as a box: • Update becomes clock().

  13. ColorCache • Problems with box model: • Half cycle latencies are not supported. • Latencies larger than 1 for fetch/allocate can generate problems. • Fetch/Allocate are not in order: • required for avoiding inanition!!!) • Fetch/Allocate success is reported 1+ cycle too late. • Could help hide conflict misses. • Force in-order fetch/allocate: • Any fetch/allocate request after a fetch/allocate that failed is rejected until the first one can be done. • Serializes. Adds latency. • Add a priority system.

  14. fetchA fetchB fetchA not accepted fetchA not accepted fetchA fetchA fetchB accepted fetchB accepted fetchB fetchC fetchA not accepted fetchA not accepted fetchA fetchA fetchC accepted fetchC

  15. ColorCache • Case analysis: • Fetch A and Fetch B different: • Fetch A and Fetch B are the same line: • Both must wait. • Order is not important. • Fetch A and Fetch B are not the same line: • Fetch A and Fetch B go to the same cache line (aliasing): • If cache line is reserved for both, both wait. • If cache line is unreserved for B A will have to wait even further. Worst case in example. • Order is not important. • Fetch A and Fetch B go to different lines: • A waits, B continues. • Could help hide latency until line for A is available. • Order is not important.

  16. ColorCache • Case analysis: • Fetch A and Fetch B are equal: • Fetch A and Fetch are from different triangles. • Order important!!! • If latency is larger than 2 then more fetched addresses must be taking into account!!!!

  17. ColorWrite • Tested a simple blend mode.

  18. Next Week • Z Test box. • Fast Color Clear (without compression). • Trace statistics.

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