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Evolvable Hardware (EHW). Topic Review S08*ENGG*6530 Antony Savich. Topic Review Outline. Motivation Concept details Problems and bottlenecks General applications Personal Retrospect Conclusion Design project summary. References.

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Evolvable hardware ehw

Evolvable Hardware(EHW)

Topic Review


Antony Savich

Topic review outline
Topic Review Outline

  • Motivation

  • Concept details

  • Problems and bottlenecks

  • General applications

  • Personal Retrospect

  • Conclusion

  • Design project summary

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  • Jim Torresen, An Evolvable Hardware Tutorial. In proc. of 14th International Conference on Field Programmable Logic and Applications (FPL'2004), August 2004, Antwerp - Belgium

  • P Haddow, G Tufte, P Van Remortel, Evolvable hardware: pumping life into dead silicon. In OnGrowth, Form and Computers.Sanjeev Kumar, Peter J. Bentley, Editors.Elsevier, 2003

  • Langdon, W.B. and Gustafson, S. (2005) Genetic Programming and Evolvable Machines: five years of reviews. Genetic Programming and Evolvable Machines, 6 (2). pp. 221-228. Springer, 2005

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What is evolvable hardware
What is Evolvable Hardware?

  • EHW is hardware which is generated or regenerated by special means

  • Goal: improve circuit performance parameters via dynamic autonomous regeneration

    • speed, area, power, output quality

  • Hardware Auto Evolution

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What do we normally do
What do we normally do?

  • Hardware engineering

    • Application analysis

    • Requirement specification

    • Circuit design (RTL, layout, routing)

    • Test suite formulation

    • Circuit verification and validation

      • Simulation

      • Hardware

    • Field performance evaluation

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What do we normally do1
What do we normally do?

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Why should we bother
Why should we bother?

  • From design specification on,

    • 85% (approx) of human time is spent on product (circuit) generation

  • Design complexity exponentially increases

    • Easy to hierarchaly specify

    • Difficult to optimize as a whole

  • Human time = expensive

  • Machine time = cheap…….

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Why should we bother1
Why should we bother?

  • Sizing limitation is not valid (Moore’s law)

    • ~1billion transistors per chip (Intel 2006)

    • How much is this better than ~100million tr. chips?

  • Designability is the current hurdle

  • Nowadays, improvement in transistor count does not equate to a similar functional or performance improvement, the gap grows…

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What is the benefit
What is the benefit?

  • If it were possible to evolve inefficient circuits…

  • The circuits created by evolution can be:

    • much simpler than human creations

    • not always comprehendible by humans

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By autoevolution we get
By autoevolution we get…

  • Reduced complexity, smaller circuits

    • In turn helps simplify the evolutionary process

  • More efficient circuits

  • Better performing circuits

  • New ideas and innovation

  • At the expense of machine time…

    gives us extra time to do other things

    than do boring circuit design?

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How do we do it
How do we do it?


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How do we do it1
How do we do it?

  • Usually implies evolutionary techniques:

    • Genetic Algorithms

    • Genetic Programming

    • Evolutionary Programming

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How do we do it2
How do we do it?

  • Can be applied to various circuits

    • Digital (commercial or custom)

    • Analog

  • Off-line or on-line evolution

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How do we do it3
How do we do it?

Use requirements


using defined




Implement on



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How do we do it4
How do we do it?


Need to map a circuit description (phenotype)

to an evolutionary technique description (genotype)

How do we represent a circuit?


using defined


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How fpgas are relevant
How FPGAs are relevant?

  • FPGAs are a natural

    example of reconfigurable

    digital technology

  • Can use the programming bitstream as the genotype directly

  • Can rapidly reconfigure to fit new solutions

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How do we do it5
How do we do it?

Need to evaluate

generated circuits

(typically many)

Assign a fitness


How would you normally

evaluate a circuit?

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Evaluation methods
Evaluation methods

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How do we do it6
How do we do it?

What are the evaluation

criteria for fitness?

Use requirements

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Problem redefinition
Problem Redefinition

  • Sometimes…

  • The task of finding a solution is redefined as a task of

    • Specifying the problem

    • Representing the solution

  • Sometimes, one is not easier than the other

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How do we do it7
How do we do it?

This step depends on the algorithm you choose,

In EHW this is typically GA (genetic algorithms)


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Genetic algorithm
Genetic Algorithm

Initial circuit population using

a chosen representation




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A cycle of evolution
A cycle of evolution

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Issues by design
Issues by design…

  • Using FPGAs leads naturally to direct mapping (genotype – phenotype)

    • Creates a search space explosion for larger circuits

  • Indirect mapping – reduces genotype description vs. phenotype requirements

    • Less information in genotype, not all phenotypes are mapped (best solution may be skipped)

    • Changes complexity of finding a best solution into complexity of finding the right mapping to include it

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Issues by design1
Issues by design…

  • Representation of genes – quick failure

    • If short, 1’s or 0’s, a single bit mutation may lead to complete circuit failure

    • It’s difficult to encode genes in a genotype such that a small gene change will result in small functionality change

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Issues by design2
Issues by design…

  • Technological evolution is a problem

    • Better flexibility means increased granularity

    • Increased complexity means larger phenotype

    • Larger phenotype means slower configuration times

    • New heterogeneous FPGA features pose mapping difficulties – not EHW friendly.

  • Complexity of system means complexity of fitness functions, longer evaluation times

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  • ‘Virtual’ FPGAs are possible:

    • Reduce genotype by simplifying routing choices; logic component choices

    • Can be mapped onto commercial FPGAs

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  • Development of EHW friendly features

    • Map only the features that are suitable for evolution

  • Partially evolvable systems

    • Design most of the system (fixed portion)

    • Allow only a portion to be evolved

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An interesting application
An Interesting Application

  • On-line evolutionary systems:

    • Create competing nodes

    • Operate one in real time

    • Evolve others in parallel

    • Another reaches maturity - swap

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Personal retrospective 1
Personal Retrospective: 1

  • On-line HW/SW evolvable system:

    • Why only require hardware execution vs. software processing?

    • Why only evolve hardware?

  • The key – hardware/software cohabitation within an on-line self-evolvable system.

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Personal retrospective 11
Personal Retrospective: 1

Evolving a




Scheduled for


Load monitor & scheduler

Task set {1..n}

Task set {1..m}





With current advances in self-reconfiguration technology

and device size, this is all possible as a SoC!

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Personal retrospective 2
Personal Retrospective: 2

  • Current research:

    Neural Network (ANN) implementations

    • Rough model of the brain

    • ANNs provide approximating solutions to problems

    • ANNs are trained on a sample of the problem space

  • Quality of results highly depends on parameters used in constructing ANN:

    • Topology (number and type of neurons)

    • Arithmetic representation

    • Learning function

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Personal retrospective 21
Personal Retrospective: 2

  • Fitness determined by training a configuration

  • Training is expensive, best done in hardware (currently FPGA), many configs to train

  • This process can benefit from automated design evolution, the technology is directly correlated with EHW methods:

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Summary ehw
Summary: EHW





Encoded by

Represented by

Need a









Implemented on

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Topic conclusion
Topic Conclusion

  • Evolvable Hardware – great circuits made easy

    (in theory)

  • Typically Genetic Algorithm is used to evolve

  • Rephrases the “circuit design” problem into the “pheno-genotype... mapping” problem.

  • Currently, can evolve small circuits

  • New hardware not friendly

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Course project direction
Course Project Direction

  • Take an existing architecture

    • monolithic, full hardware acceleration

    • a type of ANN for this project

  • Use Tensilica tools

  • Profile and map portions of hardware to produce:

    • software execution + smaller accelerator

  • Goal: compare resulting performance vs. consumption of FPGA resources.

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Thank you

S. Dali, Man with His Head Full of Clouds, 1936

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