Loading in 2 Seconds...
Loading in 2 Seconds...
Simulated Evolution Algorithm for Multi-Objective VLSI Netlist Bi-Partitioning. Sadiq M. Sait, Aiman El-Maleh, Raslan Al Abaji King Fahd University of Petroleum & Minerals Dhahran, Saudi Arabia http://www.kfupm.edu.sa 27 th May, ISCAS-2003, Bangkok, Thailand. Outline. Introduction
Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author.While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server.
Sadiq M. Sait, Aiman El-Maleh, Raslan Al Abaji
King Fahd University of Petroleum & Minerals
Dhahran, Saudi Arabia
27th May, ISCAS-2003, Bangkok, Thailand
Key CAD Capabilities
SimulationVLSI Technology Trends
The challenges to sustain such a fast growth to achieve giga-scale integration have shifted in a large degree, from the process of manufacturing technologies to the design technology.
VLSI design process is carried out at a number of levels.
Physical design converts a circuit description (behavioral/structural), into a geometric description. This description is used to manufacture a chip.
System Level Partitioning
Board Level Partitioning
Chip Level Partitioning
path : SE1 C1C4C5SE2.
Delay = CDSE1 + CDC1+ CDC4+ CDC5+ CDSE2
CDC1 = BDC1 + LFC1 * ( Coffchip + CINPC2+ CINPC3+ CINPC4)
The average dynamic power consumed by CMOS logic gate in a synchronous circuit is given by:
Ni is the number of output gate transition per cycle (Switching Probability)
load capacitance = Load Capacitances before Partitioning + load due to off chip capacitance
Total Power dissipation of a Circuit:
Weighted Sum Approach
Where Oiand Ciare lower bound and actual cost of objective “i”
i(x) is the membership of solution x in set “good ‘i’ ”
giis the relative acceptance limit for each objective.
A good partitioning can be described by the following fuzzy
IF solution has
short delay AND
THENit is a good solution
The above rule is translated to AND-like OWA
Represent the total Fuzzy fitness of the solution, our aim is to Maximize this fitness
Respectively (Cutset, Power, Delay, Balance) Fitness
Algorithm Simulated evolution
Start with an initial feasible Partition S
Evaluation :Evaluate the Gi (goodness) of all modules
For each Vi (cell) DO
if Random Rm > Gi then select the cell
Allocation:For each selected Vi (cell) DO
Move the cell to destination Block.
Until Stopping criteria is satisfied.
Return best solution.
di: set of all nets, Connected and not cut.
wi : set of all nets, Connected and cut.
Vi is the set of all nets connected and Ui is the set of all nets connected and cut.
Ki: is the set of cells in all paths passing by cell i.
Li: is the set of cells in all paths passing by cell i and are not in same block as i.
IF Cell ‘i’ is near its optimal Cut-set goodness as compared to other cells
THEN it has a high goodness.
near its optimal power goodness
compared to other cells
near its optimal net delay goodness as compared to other cells
OR T(max)(i) is much smaller than Tmax
Tmax :delay of most critical path in current iteration.
T(max)(i) :delay of longest path traversing cell i.
Xpath= Tmax / T(max)(i)
Respectively (Cutset, Power, Delay ) goodness.
ISCAS 85-89 Benchmark Circuits
Experimental Results: SimE versus TS and GA