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Simulated Evolution Algorithm for Multi-Objective VLSI Netlist Bi-Partitioning. Sadiq M. Sait, Aiman El-Maleh, Raslan Al Abaji King Fahd University of Petroleum & Minerals Dhahran, Saudi Arabia 27 th May, ISCAS-2003, Bangkok, Thailand. Outline. Introduction

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simulated evolution algorithm for multi objective vlsi netlist bi partitioning

Simulated Evolution Algorithm for Multi-Objective VLSI Netlist Bi-Partitioning

Sadiq M. Sait, Aiman El-Maleh, Raslan Al Abaji

King Fahd University of Petroleum & Minerals

Dhahran, Saudi Arabia

27th May, ISCAS-2003, Bangkok, Thailand

  • Introduction
  • Problem Formulation
  • Cost Functions
  • Proposed Approaches
  • Experimental results
  • Conclusion
vlsi technology trends




Design Characteristics









Key CAD Capabilities



VLSI Technology Trends

The challenges to sustain such a fast growth to achieve giga-scale integration have shifted in a large degree, from the process of manufacturing technologies to the design technology.

the vlsi chip in 2006

Technology 0.1 um

Transistors 200 M

Logic gates 40 M

Size 520 mm2

Clock 2 - 3.5 GHz

Chip I/O’s 4,000

Wiring levels 7 - 8

Voltage 0.9 - 1.2

Power 160 Watts

Supply current ~160 Amps

The VLSI Chip in 2006


Power consumption

Noise immunity





vlsi design cycle
VLSI Design Cycle

VLSI design process is carried out at a number of levels.

  • System Specification
  • Functional Design
  • Logic Design
  • Circuit Design
  • Physical Design
  • Design Verification
  • Fabrication
  • Packaging Testing and Debugging
physical design
Physical Design
  • The physical design cycle consists of:
  • Partitioning
  • Floorplanning and Placement
  • Routing
  • Compaction

Physical design converts a circuit description (behavioral/structural), into a geometric description. This description is used to manufacture a chip.

why do we need partitioning
Why do we need Partitioning ?
  • Decomposition of a complex system into smaller subsystems.
  • Each subsystem can be designed independently speeding up the design process (divide-and conquer-approach).
  • Dividing a complex IC into a number of functional blocks, each of them designed by one or a team of engineers.
  • The partitioning scheme has to minimize the interconnections between subsystems.
levels of partitioning
Levels of Partitioning


System Level Partitioning


Board Level Partitioning


Chip Level Partitioning


/ Blocks

classification of partitioning algorithms
Classification of Partitioning Algorithms

Partitioning Algorithms

Group Migration

Iterative Heuristics




  • Spectral
  • Multilevel Spectral
  • Lawler et al.
  • Vaishnav
  • Choi et al.
  • Jun’ichiro et al.
  • Kernighan-Lin
  • Fiduccia-Mattheyeses (FM)
  • Multilevel K-way Partitioning
  • Simulated annealing
  • Simulated evolution
  • Tabu Search
  • Genetic
  • Need for Power optimization
  • Portable devices
  • Power consumption is a hindrance in further integration
  • Increasing clock frequency
  • Need for delay optimization
  • In current sub micron design wire delay tend to dominate gate delay.
  • Larger die size imply long on-chip global routes, which affect performance
  • Optimizing delay due to off-chip capacitance
  • Design a class of iterative algorithms for VLSI multi-objective partitioning.
  • Explore partitioning from a wider angle and consider circuit delay, power dissipation and interconnect in the same time, under a given balance constraint


  • Power cost is optimized
  • Delay cost is optimized
  • Cutset cost is optimized


  • Balanced partitions to a certain tolerance degree (10%)
problem formulation
Problem formulation
  • The circuit is modeled as a hypergraph H(V,E), where V ={v1,v2,v3,… vn}is a set of modules (cells).
  • And E = {e1, e2, e3,… ek} is a set of hyperedges. Being the set of signal nets, each net is a subset of V containing the modules that the net connects.
  • A two-way partitioning of a set of nodes V is to determine two subsets VA and VB such that VA U VB = V and VAVB = 

cutset = 3

  • Based on hypergraph model H = (V, E)
  • Cost 1: c(e) = 1 if e spans more than 1 block
  • Cutset = sum of hyperedge costs
  • Efficient gain computation and update
delay model
Delay Model

path : SE1 C1C4C5SE2.

Delay  = CDSE1 + CDC1+ CDC4+ CDC5+ CDSE2

CDC1 = BDC1 + LFC1 * ( Coffchip + CINPC2+ CINPC3+ CINPC4)


The average dynamic power consumed by CMOS logic gate in a synchronous circuit is given by:

Ni is the number of output gate transition per cycle (Switching Probability)

load capacitance = Load Capacitances before Partitioning + load due to off chip capacitance

Total Power dissipation of a Circuit:

unifying objectives by fuzzy logic
Unifying Objectives by Fuzzy logic

Weighted Sum Approach

  • Problems in choosing weights.
  • Need to tune for every circuit.
  • Imprecise values of the objectives
    • best represented by linguistic terms that are basis of fuzzy algebra
  • Conflicting objectives
  • Operators for aggregating function
fuzzy logic for multi objective function
Fuzzy logic for Multi-objective function
  • The cost to membership mapping
  • Linguistic fuzzy rule for combining the membership values in an aggregating function
  • Translation of the linguistic rule in form of appropriate fuzzy operators
  • And-like operators: Min operator  = min (1, 2)
    • And-like OWA: = * min (1,2) + ½ (1-) (1+ 2)
    • Or-like operators Max operator  = max (1, 2)
    • Or-like OWA: = * max (1,2) + ½ (1-) (1+ 2)
      • Where  is a constant in range [0,1]
membership functions
Membership functions

Where Oiand Ciare lower bound and actual cost of objective “i”

i(x) is the membership of solution x in set “good ‘i’ ”

giis the relative acceptance limit for each objective.

fuzzy linguistic rule
Fuzzy linguistic rule

A good partitioning can be described by the following fuzzy


IF solution has

small cutsetAND

low powerAND

short delay AND

good Balance.

THENit is a good solution

fuzzy cost function
Fuzzy cost function

The above rule is translated to AND-like OWA

Represent the total Fuzzy fitness of the solution, our aim is to Maximize this fitness

Respectively (Cutset, Power, Delay, Balance) Fitness

simulated evolution
Simulated Evolution

Algorithm Simulated evolution


 Start with an initial feasible Partition S


Evaluation :Evaluate the Gi (goodness) of all modules

Selection :

For each Vi (cell) DO


if Random Rm > Gi then select the cell

End For

Allocation:For each selected Vi (cell) DO


Move the cell to destination Block.

End For

Until Stopping criteria is satisfied.

Return best solution.


cut goodness
Cut goodness

di: set of all nets, Connected and not cut.

wi : set of all nets, Connected and cut.

power goodness
Power Goodness

Vi is the set of all nets connected and Ui is the set of all nets connected and cut.

delay goodness
Delay Goodness

Ki: is the set of cells in all paths passing by cell i.

Li: is the set of cells in all paths passing by cell i and are not in same block as i.

final selection fuzzy rule
Final selection Fuzzy rule

IF Cell ‘i’ is near its optimal Cut-set goodness as compared to other cells



THEN it has a high goodness.

near its optimal power goodness

compared to other cells

near its optimal net delay goodness as compared to other cells

OR T(max)(i) is much smaller than Tmax

fuzzy goodness
Fuzzy Goodness

Tmax :delay of most critical path in current iteration.

T(max)(i) :delay of longest path traversing cell i.

Xpath= Tmax / T(max)(i)

Respectively (Cutset, Power, Delay ) goodness.

experimental results
Experimental Results

ISCAS 85-89 Benchmark Circuits

sime results were better than ts and ga with faster execution time
SimE results were better than TS and GA, with faster execution time.

Experimental Results: SimE versus TS and GA

conclusion re write this
Conclusion :Re-write this
  • The present work successfully addressed the important issue of reducing power and delay consumption in VLSI circuits.
  • The present work successfully formulate and provide solutions to the problem of multi-objective VLSI partitioning.
  • TS partitioning algorithm outperformed GA in terms of quality of solution and execution time.