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Heavy ion irradiation of ALTERA APEX FPGAs

Heavy ion irradiation of ALTERA APEX FPGAs M. Ceschia 1 , S.–C. Lee 2 , C. Wan 2 , M. Bellato 1,3 , M. Menichelli 4 , A. Papi 4 , J. Wyss 3,4 and A. Paccagnella 1,3 1 Dipartimento di Elettronica e Informatica, Università di Padova, via Gradenigo 6a, 35131 Padova, Italy

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Heavy ion irradiation of ALTERA APEX FPGAs

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  1. Heavy ion irradiation of ALTERA APEX FPGAs M. Ceschia1, S.–C. Lee2, C. Wan2, M. Bellato1,3, M. Menichelli4, A. Papi4, J. Wyss3,4 and A. Paccagnella1,3 1 Dipartimento di Elettronica e Informatica, Università di Padova, via Gradenigo 6a, 35131 Padova, Italy 2 Institute of Physics, Academia Sinica, Taipei 11529, Taiwan 3 Istituto Nazionale di Fisica Nucleare – Sez. Padova, via Marzolo 8, 35131 Padova, Italy 4 Istituto Nazionale di Fisica Nucleare – Sez. Perugia, via A. Pascoli, 06100 Perugia, Italy 5 Dipartimento di Fisica, Università di Padova, via Marzolo 8, 35131 Padova, Italy

  2. Outline • Introduction • Experimental set-up • SEFI’s in FPGA’s • DC supply current during irradiation • Cross Section • Conclusions

  3. Introduction • Slow evolution of rad-hard devices • Rapid evolution of CMOS technology / COTS FPGA’s • Evolution of EDA tools and IP industry Use of commercial FPGA’s in radiation harsh environments Necessity to perform radiation tests on large FPGA’s (usually SRAM-based) and to develop software error detection and mitigation techniques

  4. Experimental /1 DEVICE UNDER TEST: • ALTERA APEX FPGA: EP20K400EBC652-1 • 400,000 equivalent gates • 16,000 Logic Elements • 100 Embedded System Blocks • 213,000 Embedded RAM bits • 652 pin Ball Grid Array (BGA) package • CMOS SRAM configuration memory

  5. Experimental /2 RADIATION SOURCES: • Heavy ions from Tandem van der Graaff accelerator: From 12C, E=88 MeV, LET= 1.6 MeVcm2/mg to 197Au, E=278 MeV, LET= 78 MeVcm2/mg • Depending on the ion species the flux has been set between 15 ions/cm·s and 10,000 ions/cm·s MEASUREMENTS: • SEU / SEFI rate by monitoring signals from FPGA under test • SEL rate by monitoring supply current and turning off the power supply when Icc>800 mA • Supply current during irradiation

  6. 16 bit SHIFT reg. CLK 40 MHz Compare Error Latch Q1 16 bit SHIFT reg. TMR Signal gen. (Counter) TRIG Load Data Compare Q2 Error Latch 16 bit SHIFT reg. TMR Compare Q3 Error Latch 16 bit SHIFT reg. FPGA configuration under test Design has been fully implemented in the FPGA under test

  7. TRIG Q1 Q2 Q3 Output signals • SEFI’s happen long before any observable SEU in the flip-flops of the SR • We introduce the definition of First Error and Last Error: First Error (FE) Last Error (LE)

  8. 10-2 10-3 Device Cross Section (cm2) 10-4 10-5 0 5 10 15 20 Measurement # Device Cross Section of First Error 160 MeV Si ions, LET=8.5 MeV cm2/mg Measurements obtained by using low fluxes (~ 15 ions/cm·s). Data show statistical dispersion over two decades

  9. 0.8 0.7 0.6 0.5 Probability density (cm-2) 0.4 0.3 Experimental Data 0.2 10-6 10-5 10-4 10-3 10-2 10-1 0.1 Gaussian Distribution 0 Device Cross Section (cm2) Probability Distribution 160 MeV Si ions, LET=8.5 MeV cm2/mg Gaussian distribution seems a reasonable model to describe the data dispersion

  10. 112 MeV F ions, LET=3.9 MeV cm2/mg 10-4 10-5 Device Cross Section (cm2) 10-6 10-7 0 5 10 15 20 Measurement # Device Cross Section of Last Error LE Cross Section is about 10-100 times lower than FE Cross Section Statistical dispersion of data is over one decade

  11. 112 MeV F ions, LET=3.9 MeV cm2/mg 10-11 10-12 Device Cross Section (cm2) 10-13 10-14 0 5 10 15 20 Measurement # LE Cross Section per bit We have evaluated the Cross Section per bit of configuration memory by supposing that all the configuration memory is corrupted when the LE is detected In an EP20K400 there are about 3,900,000 configuration bits

  12. 10-2 10-3 10-4 Device Cross Section (cm2) 10-5 10-6 10-7 0 20 40 60 80 LET (MeV cm2/mg) 10-8 Device Cross Section (FE and LE) The difference between FE and LE Cross Section is almost constant and more than one order of magnitude First Error Last Error

  13. 10-9 10-10 10-11 Device Cross Section (cm2/bit) 10-12 10-13 10-14 0 20 40 60 80 LET (MeV cm2/mg) Cross Section per bit Weibull fit: F(L)=Fsat (1- exp{-[(L-L0)/W]s}) Fsat=8·10-12 cm2 L0=0.1 MeV · cm2/mg W=7 s=3.5 Weibull fit

  14. 10-1 10-2 10-3 10-4 Device Cross Section (cm2) Weibull fit 10-5 10-6 10-7 10-8 0 20 40 60 80 LET (MeV cm2/mg) Device Cross Section (taken from SEL @ 800 mA) Weibull fit: F(L)=Fsat (1- exp{-[(L-L0)/W]s}) Fsat=3·10-3 cm2 L0=1 MeV · cm2/mg W=25 s=4.5

  15. 650 600 550 500 450 Icc (mA) 400 350 300 0 4·105 8·105 1.2·106 1.6·106 2·106 250 Fluence (cm-2) 200 Supply Current / 1 112 MeV F ions, LET=3.8 MeV cm2/mg Supply current increases gradually during irradiation (no SEL, seemingly but likely due to degradation of the configuration memory)

  16. 800 700 SEL? SEL? NO SEL 600 Icc (mA) 500 400 300 200 0 4·105 8·105 1.2·106 1.6·106 2·106 Fluence (cm-2) Supply Current / 2 160 MeV O ions, LET=8.5 MeV cm2/mg Sometimes supply current sudden increases => SEL?

  17. 10-2 10-3 10-4 Device Cross Section (cm2) 10-5 10-6 10-7 10-8 0 20 40 60 80 LET (MeV cm2/mg) Device Cross Section (from FE, LE and P.S. switch off) Weibull Fit • (FE) > (LE) always First error • (FE) > (Icc>800mA) • when LET<20 Last error • (FE) < (Icc>800mA) • when LET>20 Power Supply switched off (Icc>800mA)

  18. Conclusions • Heavy ion testing of Apex Altera FPGA’s • Circuits based on four Shift Registers have been designed to test the single event effects • Only SEFI errors have been detected; destructive SEL was avoided by using a protection circuit • These SEFI’s are due to SEU in the configuration memory • Supply current increase: both gradual and step-like (SEL’s?) have been observed • Cross Section per bit has been estimated by supposing that last error corresponds to entire memory corruption

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