TPC/HBD electronics

1. TPC/HBD electronics • Possible system diagrams for TPC and HBD • Channel count and data volume • Cost of building ASIC • Alice’s ALTRO chip example • For their TPC readout

2. TPC READOUT METHOD 1 AMU store the signal every 40 MHz. When L1 trigger arrive, we will send the event to the digitizer No. of AMU cell need to cover L1 delay + 5 event buffer => 1000 cells 1 event = 160 cells if we run 40 MHz Need to build address manager

3. TPC READOUT METHOD 2 The signal is directly digitized in a 20-40 MHz 8-9 bits ADC. A buffer will store the digitized data till corresponding L1 trigger. No. of L1 delay buffer need to cover L1 delay + 5 event buffer => 1000 ( 40 MHz) The FEM will zero suppressed L1 accepted event on the detector by at least factor of 20. The FEM needs to participate in the BUSY logic

4. Possible HBD readout 1 Challenge for HBD electronics Low mass requirement for the electronics within active area Need to measure charge and time (few ns) hard to bring raw or amplified signal out to the edge of the detector too fewer channels for ASIC development On detector ASICs 10 MHz

5. Possible HBD readout 2 If all the charge arrives in the “same time”, we could have a longer shaping time. We will obtain few ADC samples on the rising edge of the pulse. The T0 of the pulse can be determined by a linear fit from the leading edge samples. On detector ASICs

6. Data Volume and Readout Speed for TPC Number of channels Aplane = p (552 - 202) = 8247 cm2 Apad = 1.0 x 0.2 = 0.2 cm2 Npad = 8247/0.2 = 41,233 x 2 = ~ 80K chs Readout Speed in PHENIX Buffer size < 40 beam clock ticks 40 x 100 ns (10 MHz) = 4 msec (EMCAL pushes this to 6.4 msec) Readout time < 40 msec (25 KHz in DCM) 800 Kb => 6.4 x 106 bits/40 x 10-6 sec = 1.6 x 1011 bits/sec = 160 Gbits/sec (20 Gb/sec) => 160 1Gbit fibers (TEC has 128) => 40 DCMs (TEC has 28) Data Volume 4 msec/20 ns => 200 time samples (8 bits) 80K x 200b ~ 16 Mb Assume zero suppression of 1/20 => 800 Kb (actual hit rate gives 80 Kb => 1/200) Trigger Expect actual trigger rate in pp to be ~104 Hz at L = 2 x 1032 (trigger rate of interesting events including W,Z,charm is only ~ 103 Hz) If data volume after final zero suppression is 80 Kb, then 80 Kb x 104/sec => 800 Mb/sec => need Level 3 trigger

7. HBD channel count/ Data volume • HBD is located on the outer shell of the HBD/TPC. • Channel count ~ 4500 channels • Occupancy in AU-AU central is 20% assuming 4 layers of silicon with 1% radiation length

8. Fabrication cost of Custom ASIC in MOSIS D: digital M: mixed signal ALTRO chip size Assume 2 small chip size run, 2 med. size run and 2 final prototype --- The cost of prototype will cost to 250K – 300K per chip.

9. ALICE TPC FEE overview

10. Overall diagram for ALTRO chip

11. The TPC pad size is 2mm X 1 cm. The total area for 16 channels is 320 mm2. The Alice die area is 7.7mm X 8.3 mm = 64 mm2.

12. Steps need to be taken next • R&D need start quickly on ASIC works, especially on the ADC. • We need to talk to some of CERN people on their ADC design. • Need to quickly decide the readout architecture. • The TPC readout method could impact how we design the next generation DCM.