ISCUG: Virtual Prototyping

1. ISCUG: Virtual Prototyping From evolution to revolution Kevin Smart 15-Apr-2013

2. A proud Scotsman  • Kevin Smart • Director, R&D. System-Level Solutions at Synopsys • Responsible for Virtual Prototyping delivery • Joined Virtio in 2001, acquired by Synopsys in 2006 • Delivered >80 virtual platforms, >3000 TLMs • Introduced first commercial SystemC TLM-2.0 model library in 2008 • Accelerating development of ARM and automotive SystemC virtual platforms, with Virtualizer Development Kits (VDKs)

3. Outline As embedded system complexity grows, with software playing a bigger role, virtual prototyping will face fresh challenges, including model availability and performance The last 10 years has seen virtual prototyping evolve from early adoption to mainstream, from proprietary technologies to standardizing on SystemC We will discuss real world examples of how companies are using SystemC based virtual platforms for early software development Learn about reducing modeling time, creating efficient virtual prototypes, and the paradigm shift required to enable a modeling ecosystem

4. What is a Virtual Prototype? • Fully functional software model of complete systems • SoC, board, I/O, user interface • Executes unmodified production code • Drivers, OS, and applications • Runs fast • Boots OS in seconds • Highest debugging efficiency through full system visibility and control • Supports multi-core SoCsdebug • Easy deployment Software Stack Virtual Prototype

5. Why Prototype? Right Architecture, Earlier SW Development, HW/SW Integration & System Validation Standard Project Flow Without Prototyping Spec Freeze Tape Out Silicon Project Finished SoC Hardware Development Manufac- turing Arch Design Software Development, HW/SW Integration & System Validation Early Time-to-Market with Prototyping Spec Freeze Tape Out Silicon Project Finished SoC Hardware Development Manufac- turing Arch Design Software Development, Integration & System Validation Gained TTM

6. Virtual Prototyping Evolution How we got where we are today

7. The Innovators, the Turnkey era 2002- • Post-silicon use cases emerged first • Compared to today it was easier to model an entire design e.g. Intel Lubbock, TI OMAP1510 • SoCs: 1-2 processor cores • Fewer discrete components • Could run production software images in automated regressions • Avoid waiting 15-mins to reprogram the Flash • Large disparity in performance, host PC vs. virtual target • Interpreted ISSs were fine

8. Early adoptors 2004- • It’s all about Early • With post-Si value established it was realized there could be huge schedule benefits from early software development • Especially for ROM code, secure software that resides on-chip • Needs to be correct first-time, avoid expensive respin • And even Earlier • Incremental development aligned with software schedules

9. Best Practices - Incremental Development Enabling Software Bringup In Lock Step with SoC Design Sensor software ARM Cortex MPCore ARM Cortex MPCore ARM Cortex MPCore ARM Cortex MPCore Display Display Multimedia software Graphics Graphics Graphics software L2 L2 Imaging Imaging Driver development ICT ICT Peripheral -als Audio Audio Security Security Peripheral -als Peripheral -als Sensors Sensors Video Video OS base port Security software Flash Flash IO IO Memory Controller Memory Controller Power & Clocks Power & Clocks Boot code Modeling Team • Software ready before silicon availability • Requires tight planning alignment between modeling and software teams Software Development Team

10. Deliver to OEM Hardware Availability Virtual Platform UsageA Case Study # of users Early (Pre-Si) Software Development

11. From Turnkey to Collaborative 2005 • As Complexity grew, modeling effort increased • Collaborative development started to make more sense • Customer modeling teams were established and trained • Increased complexity, multi-core, required greater performance • JIT ISS technology • Other use cases explored • Optimizing software for power • Trend-based performance analysis

12. Move to open standards 2006-2007 • Acquisition by Synopsys • Standardization- tools updated to support SystemC • Key contributor to TLM-2.0 (focus on performance: DMI, temporal decoupling) 2008 • Ratification of TLM-2.0 • Release of DesignWare System-Level Library, first commercial TLM-2.0 compliant model library

13. Acquisitions 2010 • VaST • Acquired fast timing-approximate technology • Automotive vertical • CoWare • SystemC based Architecture Performance Analysis/Optimization • Hardware/software combined analysis • SystemCModeling Library (SCML2), to simplify creation of TLMs

14. Consolidation 2011-2012 • Virtualizer • New tool with enhanced SystemC kernel designed to support existing portfolio of models, strengthening debug and analysis • Fast-Timed Models • VaST technology brought into SystemC 2012-2013 • Virtualizer Development Kits(VDKs) • Extensible VPs + Debug/Analysis + Sample Software • ARM big.LITTLE, using ARM Fast Models • ARMv8, agreement with ARM • Automotive MCUs- Freescale, Renesas

15. TLMCreator Simplified Model Creation Flow GUI Proprietary Format Tcl Script Tcl API Data Model Round tripping IP-XACT Import Excel Code Generator Proprietary Format TLM-2.0 Model (+ docs and tests) IDE/Assembly Tools Page 15

16. VP/VDK Development Flow Start ‘New Platform’ System Specification Platform Creator Component Libraries Component Tests Platform Assembly Virtual Platform System & Integration Testing Plug Tests into Test Framework Develop System Tests Perform Integration & SystemTesting AutomaticTest Report Licensing & Packaging Releasing Auto-building Final Release Testing Release Drop

17. VDK Creation and Use Flow VDK Creation Flow Software Tool Interfaces Model Libraries Virtualizer: VP Creation VDK Use Component Modeling VDKs • Design Tasks: • SW-driven verification • SoC HW/SW integration • SW development • System validation & test • Supply chain enablement HW/SW Debug & Analysis Tools Assembly Virtual Prototype Block Creation Flows Debugging Co-Simulation & External Connectivity

18. Many factors influence performance Simulation Speed simulation breakpoints abstraction eSW breakpoints temporal accuracy modeling ISS speed memory configuration target cache on/off watchpoints temporal decoupling DMI handling # of synchronization points coding style interconnect modeling JIT engine i/o (tracing, logging, semi-hosting, …) PEQ cache/MMU models clock modeling compiler (and flags) JIT cache host OS host machine and cache alignment DMI vs front door access dynamic clocks quantum static design complexity scaling beat/burst timing rounding effective ability to profile and interpret results eSW image (spatial/temporal locality, peripheral accesses, …) Page 18

19. VPExplorer Which model is slowing down the simulation? Process Trace: Which SystemC threads eating most time? Hot Spot View: Where are the slow areas? When is a Quantum Broken? Page 19

20. Achieving Prototyping Productivity Model Libraries TLMCentral VPExplorer TLM Creator/VPExplorer Page 20

21. Virtual Prototyping Revolution The way forward

22. The Virtual Prototyping Urgency Page 22

23. The Virtual Prototyping Challenges • Model availability • SoCs are increasing in complexity, raising the modeling barrier • Need to lower the barrier through model reuse • IP vendors should provide quality TLMs • TLMs should be a by-product of the hardware flow • Further interfaces should be standardized • Need models for different use cases e.g. Accelerometer: file-input for driver developer vs. interactive for end-user • Licensing requires simplified • Please add your models to tlmcentral.com RST CLK IRQ TLM2 SPI TLM-2 AHB Socket TLM-2 SERIAL TX/RX

24. Model Yellow Pages

25. The Virtual Prototyping Challenges • Performance • Single-thread performance is tailing off • Need to exploit multi-core better • GPU will be a challenge (OpenGL, OpenCL, Renderscript) • Hybrid Approach

26. Natural Partition with Hybrid Approach Customer Example: Mobile Applications Processor Virtual Prototype FPGA-Based Prototype Dual Core ARM Cortex Display Audio Modem Chip Graphics L1 L1 Camera Imaging L2 ICT Touchscreen Bluetooth, GPS Audio processor Video SD controller Sensor processor Peripher -als WiFi Power & Clocks IO processor SIM card Controller Memory Controller + Rapid creation of models + High execution speed + Excellent debug access + 'Unlimited' capacity + Validation of SoC RTL + Real world I/O access + Cycle accurate RAM Battery

27. The Virtual Prototyping Challenges • Increasing value • Models should be “chatty” providing feedback to users on programming violations • Be Earlier, increase modeling productivity through tool improvements, reusable libraries • We need to provide more root cause analysis, solving embedded software challenges

28. Summary As embedded system complexity grows, with software playing a bigger role, virtual prototyping will face fresh challenges, including model availability and performance The last 10 years has seen virtual prototyping evolve from early adoption to mainstream, from proprietary technologies to standardizing on SystemC A paradigm shift is required to enable a modeling ecosystem: IP vendor models, interface standardization, simplified licensing Further tool improvements are required to reduce modeling effort, solve embedded software challenges