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A Posynomial-Based Lagrangian Relaxation Tuning Tool for Combinational Gates and Flip-Flops Sizing

A Posynomial-Based Lagrangian Relaxation Tuning Tool for Combinational Gates and Flip-Flops Sizing. Presenter: Tsung-Tse Lin Advisor: Prof. Chung-Ping Chen. Outline. Background and Motivation The Optimal Algorithm for Sizing Cyclic Sequential Circuits Experiment Result Conclusion.

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A Posynomial-Based Lagrangian Relaxation Tuning Tool for Combinational Gates and Flip-Flops Sizing

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  1. A Posynomial-Based LagrangianRelaxation Tuning Tool forCombinational Gates and Flip-Flops Sizing Presenter: Tsung-Tse Lin Advisor: Prof. Chung-Ping Chen

  2. Outline • Background and Motivation • The Optimal Algorithm for Sizing Cyclic Sequential Circuits • Experiment Result • Conclusion

  3. Previous Work • Several convex optimization methods have been proposed for sizing combinational circuits. • C.C.P. Chen et al. ”Fast and Exact Simultaneous Gate and Wire Sizing by Lagrangian Relaxation,”, in TCAD 1999 • H. Sathyamurthy et al. formulated the sequential circuit sizing problem as a nonlinear convex program using the Elmore delay model. • ”Speeding up Pipelined Circuits through a Combination of Gate Sizing and Clock Skew Optimization”, in TCAD 1998

  4. Thesis Motivation • Circuit tuning for sequential circuits • Most of the existing circuit tuning algorithms are only for combinational circuit • However, most of the VLSI circuits contain flip-flops and/or latches • Therefore, circuit tuning for sequential circuits is crucial

  5. Overall Flow

  6. Flatten the hierarchical netlist

  7. Our tool in design flow

  8. Posynomial Functions

  9. Modelling in Posynomial Form

  10. Sequential Circuits Tuning Problem Formulation C:clock, a: arrival time, D:delay, Tsetup:setup time

  11. Lagrangian Relaxation Primal Problem Lagrangian Relaxation

  12. KKT Condition for the Lagrangian Function Solution

  13. Iterative Multiplier Adjustment

  14. Algorithm Summary

  15. Experiment Results on RDC Circuits(Run PrimeTime)

  16. Conclusion • In this thesis, we propose an optimal Lagrangian relaxation based gate sizing algorithm for globally sizing industrial library based designs. • We use nonlinear convex models for accurately representing the gate delays and can size both cyclic and acyclic sequential circuits. • We can also handle the hierarchy of the synthesized netlist, and integrate our tuning tool to the standard design flow seamlessly.

  17. Q & A • Thank You

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