Gate Sizing Based on Lagrangian Relaxation

1. Gate Sizing Based on Lagrangian Relaxation Yu-Min Lee Advisor: Charlie Chung-Ping Chen

2. Functionality • Gate characterization • Propagation delay • Gate capacitance • Posynomial curve fitting • Lagrangian relaxation(LR) sizer • Automatic gate sizing • Optimality guarantee for convex programming problem

3. LR Sizer Structure Gate Lib/ HSPICE Gate Characterization Curve Fitting ISCAS Format Circuit LR Sizer

4. Gate Characterization • Use HSPICE simulator to characterize the delay of each gate, NOT, NAND, NOR, … with different sizes and load capacitance • Use HSPICE simulator to characterize the equivalent input capacitance of each gate, NOT, NAND, NOR, … with different sizes and load capacitance

5. Curve Fitting: Posynomial • Use least-square fitting to find the best posynomial curve for propagation delay, and equivalent capacitance of each gate

6. Lagrangian Relaxation • LRS (Lagrangian Relaxation Subproblem) • The optimal solution for any LRS is a lower bound of the original problem for any type of problem • There exists Lagrangian multipliers will lead LRS to find the optimal solution for convex programming problem