OpAmp (OTA) Design The design process involves two distinct activities: • Architecture Design • Find an architecture already available and adapt it to present requirements • Create a new architecture that can meet requirements • Component Design • Design transistor sizes • Design compensation network
All op amps used as feedback amplifier: If not compensated well, closed-loop can be oscillatory or unstable. damping ratio z≈ phase margin PM / 100 Value of z: 1 0.7 0.6 0.5 0.4 0.3 Overshoot: 0 5% 10% 16% 25% 37%
UGF: frequency at which gain = 1 or 0 dB PM: phase margin = how much the phase is above critical (-180o) at UGF Closed-loop is unstable if PM < 0 UGF PM
UGF GM<0 p1 p2 z1 PM<0
UGF p1 p2
UGF GM p1 p2 z1 PM
Types of Compensation • Miller - Use of a capacitor feeding back around a high-gain, inverting stage. • Miller capacitor only • Miller capacitor with an unity-gain buffer to block the forward path through the compensation capacitor. Can eliminate the RHP zero. • Miller with a nulling resistor. Similar to Miller but with an added series resistance to gain control over the RHP zero. • Self compensating - Load capacitor compensates the op amp (later). • Feedforward - Bypassing a positive gain amplifier resulting in phase lead. Gain can be less than unity.
General Miller effect v2 v1 i v2= AVv1 v1 i= v1/Z1 i i = (v1-v2)/Zf =v1(1-AV)/Zf = - v2(1-1/AV)/Zf i= -v2/Z2
Miller compensator capacitor CC C1 and CM are parasitic capacitances
DC gain of first stage: AV1 = -gm1/(gds2+gds4)=-2 gm1/(I5(l2+ l4)) DC gain of second stage: AV2 = -gm6/(gds6+gds7)=- gm6/(I6(l6+ l7)) Total DC gain: gm1gm6 AV = (gds2+gds4)(gds6+gds7) 2gm1gm6 AV = I5I6 (l2+ l4)(l6+ l7) GBW = gm1/CC
Zf = 1/s(CC+Cgd6) ≈ 1/sCC When considering p1 (low freq), can ignore CL (including parasitics at vo): Therefore, AV6 = -gm6/(gds6+gds7) Z1eq = 1/sCC(1+ gm6/(gds6+gds7)) C1eq=CC(1+ gm6/(gds6+gds7))≈CCgm6/(gds6+gds7) -p1 ≈ w1 ≈ (gds2+gds4)/(C1+C1eq) ≈ (gds2+gds4)/(C1+CCgm6/(gds6+gds7)) ≈ (gds2+gds4)(gds6+gds7)/(CCgm6) Note: w1 decreases with increasing CC
M6 M7 CC C1 CL At frequencies much higher than w1, gds2 and gds4 can be viewed as open. Total go at vo: CC gds6+gds7+gm6 CC+C1 vo Total C at vo: C1CC CL+ CC+C1 -p2=w2= CCgm6+(C1+CC)(gds6+gds7) CL(C1+CC)+CCC1
gds6+gds7 Note that when CC=0, w2 = CL As CC is increased, w2 increases also. However, when CC is large, w2 does not increase as much with CC. w2 has a upper limit given by: gm6+gds6+gds7 gm6 ≈ CL+C1 CL+C1 When CC=C1, w2 ≈ (½gm6+gds6+gds7)/(CL+½C1) Hence, once CC is large, its main effect is to lower w1, and hence lower GBW.
Also note that, in contrast to single stage amplifiers for which increasing CL improves PM, for the two stage amplifier increasing CL actually reduces w2 and reduces PM. Hence, needs to design for max CL
There are two RHP zeros: z1 due to CC and M6 z1 = gm6/(CC+Cgd6) ≈ gm6/CC z2 due to Cgd2 and M2 z2 = gm2/Cgd2 >> z1 z1 significantly affects achievable GBW.
gm6/(CL+C1) f (I6) A0 z1≈ gm6/Cgd6 w1 w2 z2≈ gm2/Cgd2 -90 No PM -180
gm6/(CL+C1) f (I6) A0 z1≈ gm6/Cgd6 z2≈ gm2/Cgd2 w1 w2 z1≈ gm6/Cc -90 No PM -180
gm6/(CL+C1) f (I6) A0 w2 z1≈ gm6/CC w1 gm1/CC -90 PM -180
It is easy to see: PM ≈ 90o – tan-1(UGF/w2) – tan-1(UGF/z1) To have sufficient PM, need UGF < w2 and UGF << z1 In such case, UGF≈ GB ≈ gm1/CC = z1 * gm1/gm6. GB < w2 GB << z1 Hence, need: PM requirement decides how much lower: PM ≈ 90o – tan-1(GB/w2) – tan-1(GB/z1)
Possible design steps for max GB • For a given CL and Itot • Assume a current share ratio q, i.e. • I6+I5 = Itot, I5 = qI6 , I1 = I2 = I5/2 • Size W6, L6 to achieve max gm6/(CL+Cgs6) which is > w2 • C1 W6*L6, gm6 (W6/L6)0.5 • Size W1, L1 so that gm1≈ 0.1gm6 • this make z1 ≈ 10*GBW • Select CC to achieve required PM • by making gm1/CC < 0.5 w2 • Check slew rate: SR = I5/CC • Size M5, M7, M3/4 for current ratio, IMCR, etc
Comment • If we run the same total current Itot through a single stage common source amplifier made of M6 and M7 • Single pole go/CL • Gain gm6/go • Single stage amp GB = gm6/CL >gm6/(CL+C1) > w2 > gm1/CC = GB of two stage amp • Two stage amp achieves higher gain but speed is much slower! • Can the single stage speed be recovered?
Other considerations • Output slew rate: SR = I5/CC • Output swing range: VSS+Vdssat7 to VDD – Vdssat6 • Min ICM: VSS + Vdssat5 + VTN + Von1 • Max ICM: VDD - |VTP| - Von3 + VTN • Mirror node approx. pole/zero cancellation • Closed-loop pole stuck near by • Can cause slow settling
When vin is short, the D1 node sees a capacitance CM and a conductance of gm3 through the diode con. So: p3 = -gm3/CM When vin is float and vo=0. gm4 generate a current in id4=id2=id1. So the total conductance at D1 is gm3 + gm4. So: z3 = -(gm3+gm4)/CM =2*p3 If |p3| << GB, one closed-loop pole stuck nearby, causing slow settling!
Eliminating RHP Zero at gm6/CC icc = vg gm6 = CCdvCC/dt vg= RZCCdvCC/dt +vcc CCdvCC/dt (gm6RZ-1)CCdvCC/dt + gm6vcc=0
For the zero at M6 and CC, it becomes z1 = gm6/[CC(1-gm6Rz)] So, if Rz = 1/gm6, z1 → For such Rz, its effect on the p1 node can be ignored so p1 remains as before. Similarly, p2 does not change very much. similar design approach.
VDD M9 M8
Another choice of Rz is to make z1 cancel w2: z1=gm6/CC(1-gm6Rz) ≈ - gm6/(CL+C1) CC+CL+C1 Rz = gm6CC CL+C1 1 (1+ ) = CC gm6
Let ID8 = aID6, size M6 and M8 so that VSG6 = VSG8 Then VSGz=VSG9 Assume Mz in triode Rz = bz(VSGz – |VT| - VSDz) ≈ bz(VSGz – |VT|) = bz(2ID8/b9)0.5 = bz(2aID6/b6)0.5(b6/b9)0.5 = bz/b6 *b6VON6 *(ab6/b9)0.5 = bz/b6 *1/gm6*(ab6/b9)0.5 Hence need: bz/b6 *(ab6/b9)0.5 =(CC+CL+C1)/CC
gm6/(CL+C1) f (I6) A0 -z1≈ w2 w1 gm1/CC -90 PM -180
With the same CC as before • Z1 cancels p2 • P3, z3, z2, not affected • P1 not affected much • Phase margin drop due to p2 and z1 nearly removed • Overall phase margin greatly improved • Effects of other poles and zero become more important • Can we reduce CC and improve GB?
A0 gm6/CL Operate not on this but on this or this z1≈ p2 z2≈ gm2/Cgd2 z4≈ gm6/Cgd6 w1 w2 -90 -180
Increasing GB by using smaller CC • It is possible to reduce CC to increase GB if z1/p2 pole zero cancellation is achieved • Can extend to gm6/CL • Or even a little bit higher • But cannot push up too much higher • Other poles, zeros • Imprecise mirror pole/zero cancellation • P2/z1 cancellation • GB cannot be too high relative to these p/z cancellation • Z2, z4, and pz=-1/RZCC must be much higher than GB
Possible design steps for max GB • For a given CL and Itot • Assume a current share ratio q, i.e. • I6+I5 = Itot, I5 = qI6 , I1 = I2 = I5/2 • Size W6, L6 to achieve max single stage GB1 = gm6/(CL+Coutpara) • Make z4=gm6/Cgd6 > (10~50)GB1 • Choose GB = aGB1, • Choose CC to make p2 ≈ GB/(10~20) • Size W1, L1 and adjust q so that gm1/CC ≈ GB • Make z2=gm2/Cgd2 > (10~20)GB • Size Mz so that z1 cancels p2 • Make sure |pz| due to Mz and CC >> GB • Make sure PM at f=GB is sufficient • Size M3/4 so that gm3/CM is > GB/(10~20) • Check slew rate, and size other transistors for ICMR, OSR, etc
Simple transistor circuits • Can use any # of ideal current or voltage sources, resisters, and switches • Use one or two transistors • Examine various ways to place the input and output nodes • Find optimal connections for • high gain • high bandwidth • high or low output impedance • low input referred noise
Single transistor configurations • It’s a four terminal device • Three choices of input node • For each input choice, there are two choices for the output node • The other two terminals can be at VDD, GND, virtual short (V source), virtual open (I source), input, or output node • Most connections are non-operative or duplicates • D and S symmetric; B not useful
2 valid input choice and 1 output choice Connection of other terminals: or Resister
Capacitor Gnd or virtual Common source
This is D To VDD Source follower
N-channel common gate p-channel common gate
Building realistic circuits from simple connections flip vertical Combine N common source
flip left-right N common source Combine to form differential pair
Vbb flip upside down to get current source load Vbb Combine to form differential amp
Can also use self biasing and convert to single ended output Replace virtual gnd by current source
two transistor connections Start with one T connections, and add a second T Many possibilities many useless some obtainable by flip and combine from one T connections some new two T connections Search for ones with special properties in terms of AV, BW, ro, ri, etc
First MOST is CS D1 connects to D2: (with appropriate n-p pairing) -kvo vo vin CS with negative gm at output node CS Push pull CS