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Time-Driven Priority Router Prototype: A FreeBSD-Based Implementation

This project presents a prototype of a Time-Driven Priority (TDP) router implemented on a PC using FreeBSD. The study identifies critical aspects, demonstrates multimedia benefits of TDP, and compares video quality with asynchronous packet switching. The architecture includes components like TDP input classifier, output buffers, scheduler, and more. Implementation challenges, consequences, and conclusions are discussed, emphasizing proof of concept and future work for performance evaluation and network testbed realization.

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Time-Driven Priority Router Prototype: A FreeBSD-Based Implementation

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  1. Politecnico di Torino Istituto Superiore Mario Boella A FreeBSD-based prototype of a Time-Driven Priority router Mario Baldi Guido Marchetto

  2. Goals • First implementation of TDP • Until now analytical studies and software simulations only • Identification of possible criticalities • Visually show TDP benefits through multimedia demonstration • Video quality with TDP vs asynchronous packet switching

  3. Network prototype topology TDP network router host

  4. Router architecture • PC based • FreeBSD operating system • Four components: • TDP input classifier • TDP output buffers (ALTQ extension) • TDP scheduler • Asynchronous input shaper(Dummynet extension)

  5. Common Time Reference (CTR) • Adopted card: Symmetricom • Periodic interrupt over the PCI bus • Programmable interrupt frequency • Each interrupt represents the beginning • of a new TF

  6. Implementation issues • Interfaces are not served at the same time • Interrupts are served with latency • Both servicing times are variable

  7. Consequences • Transmissions do not start as soon asthe TF begins • Violation of nominal time frame boundaries • Transmissions start with a variable delay • Potential bandwidth waste

  8. Facts • Latency equivalent to longer links • Interrupt and interface service latencyis low • Latency variation is absorbed by “delaying” forwarding time-frame • Interrupt and interface service latency has low variability • “EXTRA” CROSSING DELAY IN THE NODE • “EXTRA” BUFFERING IN ORDER TO HANDLE THIS DELAY

  9. Conclusions • Contribution • Proof of concept: • Algorithm and system semplicity(~1000 LOC) • PC architecture can support TDP • Future work • Performance evaluation • Realization of the network testbed and demonstration

  10. Thank you. Questions?

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