基于 FPGA 的处理器多周期时分复用功能级模拟. 清华大学计算机系高性能计算所 张悠慧 2010.10. 研究背景. 核的增加和. Cache #0. Cache #1. ……. Cache #15. Cache Controller. Memory. SRAM. SDRAM. IDE. 主要思路. Interleaved Pipeline 16xCPU. NIOSII Processor #0_MMU. NIOSII Processor #1_Cplx. NIOSII Processor #2_PCI-E. 16Clk. 1Clk.
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