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Generalized SAT-Sweeping for Post-Mapping Optimization

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## Generalized SAT-Sweeping for Post-Mapping Optimization

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**Generalized SAT-Sweeping for Post-Mapping Optimization**Tobias Welp1 Smita Krishnaswamy2 Andreas Kuehlmnn1,3 1University of Califonia at Berkeley, CA, USA 2Columbia University, NY, USA 3Coverity, Inc., San Francisco, CA, USA Date: 2012/6/29**Outline**• Introduction • Motivation • Preliminaries & Related Work • Post-Mapping Optimization (PMO) • Experimental Setup & Results • Conclusion**Introduction**• Modern synthesis flows apply a series of technology independent optimization steps followed by mapping technology library • Technology independent optimization techniques: • Pattern matching and global flow optimization [1] • BDD-based logic restructuring [2] • SAT-sweeping [4] [1] C. L. Berman and L. H. Trevillyan, “Global flow optimization in automatic logic design,” IEEE Trans. Computer-Aided Design, vol. 10, pp. 557–564, May 1991. [2] R. E. Bryant, “Graph-based algorithms for Boolean function manipulation,”IEEE Trans. Computers, vol. 35, pp. 677–691, Aug. 1986. [4] V. N. Kravets and P. Kudva, “Implicit enumeration of structural changes in circuit optimization.,” in Proceedings of the 41th ACM/IEEE Design Automation Conference, pp. 526–532, 2004**Introduction**• Technology mapping is used to bind the abstract logic network to a specific technology library • The mapping problem is known to be NP-hard, so exact solutions can only be calculated for small designs • Instead, one usually resorts to tree-mapping algorithms [6] [6] K. Keutzer, “DAGON: technology binding and local optimization by DAG matching,” in Proceedings of the 24th ACM/IEEE Design Automation Conference, DAC ’87, (New York, NY, USA), pp. 341–347, ACM, 1987.**Introduction**• Although the application of the algorithm heuristically yields good results, the design loses quality during the technology mapping, in particular if the netlist is strongly connected. • This motivates the application of optimization algorithms which are applied after mapping**Introduction**• The presented efficient and effective algorithm for post mapping optimization combines several key ideas used in logic synthesis, such as simulation based heuristics, SAT-solving, node addition and attempts to find a better implementation of each net • The presented algorithm can be considered a generalization of SAT-sweeping**Motivation**• Example**Related Work**• Post-mapping optimization for FPGAs [7] • post-mapping, LUTs + programmable routing structure as SAT instance • SAT-Sweeping [4] [8] • SAT-Sweeping + ODCs, AIGs • Node addition and removal [9] • Addition of node (AND) and removal • Fixing Design Errors with Counterexamples and Resynthesis [10] • Signatures • [7] A. Ling, D. P. Singh, and S. D. Brown, “FPGA Technology Mapping: A Study of Optimality,” in Proceedings of the 42th ACM/IEEE Design Automation Con ference, pp. 121–126, 2005. • [8] Q. Zhu, N. Kitchen, A. Kuehlmann, and A. L. Sangiovanni-Vincentelli, “SAT Sweeping with Local Observability Don’t Cares,” in Proceedings of the 43th ACM/IEEE Design Automation Conference, pp. 202–207, 2006. • [9] Y. C. Chen and W. Chun-Yao, “Node addition and removal in the presence of don’t cares,” in Proceedings of the 47th ACM/IEEE Design Automation Conference, pp. 505–210, 2010. • [10] K.-H. Chang, I. L. Markov, and V. Bertacco, “Fixing Design Errors with Counterexamples and Resynthesis,” in Proceedings of the Asia-South Pacific Design Automation Conference, pp. 944–949, 2007.**Preliminaries**• Target net n and its potential replacement alternative implementation • Arbitrary monotone gate • 1. The value at the output of the gate can be calculated by iteratively applying the same operator to all fanins and optionally applying a unary operation to the result • 2. Adding another fanin to the gate must impact the value of the gate in only one direction • Ex: NAND , XOR**Preliminaries**• The simulation vector associated with net n φ(n) • ith bit within this vector φ(n)[i]**Outline**• Introduction • Motivation • Preliminaries & Related Work • Post-Mapping Optimization (PMO) • Experimental Setup & Results • Conclusion**Post-Mapping Optimization (PMO)**• Collection of Support Nets • Random Simulation • Filtering Support Nets • Feasibility Check • Searching Candidates for Alternative Implementation • Evaluating the Value of a Replacement • Verifying the Validity of Replacements**Collection of Support Nets**• Populate S with all nets in the transitive fanin of net n which are at least d levels and at most D levels away from n • Note that a net is added to the set of support nets regardless of if it is at least d away from n if it does not have any fanins – PIs**Random Simulation**• Simulation vectors can be produced by assigning random values to the support nets and simulating only the cone of the network between the support nets and the target net • However, this allowed for unjustifiable value combinations at the support nets (SDCs) - assign random values to the primary inputs of the complete circuit • Avoid unnecessary recalculation of simulation values which have been calculated already • The network does not need to be re-simulated until changes are made to the network (TFOC of target net)**Filtering Support Nets**• Assume the added gate is an AND gate - Φ(n) = 1001 , Φ(s1) = 1101, Φ(s2) = 0111, Φ(s3) = 1001 • Improve by considering ODCs bits**Feasibility Check**• Avoid spending runtime on trying to find a candidate for an alternative implementation of the target net in case there is none using the set of filtered support nets • There is no such candidate if there exists a simulation slice for which the value of the target net cannot be obtained even if all support nets were considered • Ex: AND- gate • The conjunction of the simulation vectors of all support nets must be equivalent to that of the target net**Searching Candidates for Alternative Implementation**• Find a concrete alternative implementation of the target net guided by using the simulation vectors • Ex: AND gate • Consider ODCs**Searching Candidates for Alternative Implementation**• Priority queue initialized with S • Prefer S* with small cardinality • Fitness function • Fd for quickly finding a candidate • Fc for emphasizing on a small added gate**Evaluating the Value of a Replacement**• If the replacement deteriorates the circuit, don’t implement it • Optimize the size of the circuit under the constraint that timing does not deteriorate • If the arrival time of the target net using the alternative implementation is larger than the required time of the original target net, the delay of the circuit will deteriorate • Area gain = the complete fanout free cone in the transitive fanin of n – newly added gate**Verifying the Validity of Replacements**• Miter structure • Constrain that at least one pair of combinational outputs must be non-equivalence (output is 1) • Satisfiable = invalid • Unsatisfiable = equivalent • Tseitin-transformation [13] • [13] G. Tseitin, “On the complexity of derivation in propositional calculus,” vol. 8 of Seminars in Mathematics, Leningrad: V. A. Steklov Mathematical Institute, 1968. English translation: Studies in mathematics and mathematical logic, Part II, 1970, pp. 115-125.**Verifying the Validity of Replacements**• SDCs and ODCs • If there is a difference between original and alternative implementations which either cannot be stimulated or not observed at the output, the SAT-instance will not be satisfiable**Verifying the Validity of Replacements**• The presented exact solution can result in very excessive runtime for large circuits • It is often advantageous to consider much smaller SAT-instances which may be satisfiable if the replacement is valid but maintaining the property that it cannot be unsatisfiable if the replacement is invalid.**Verifying the Validity of Replacements**• Add only those gates to the SAT-instance, which are at most b levels away from the target net in both fanin and fanout direction • b = window size in SAT-Instance**Outline**• Introduction • Motivation • Preliminaries & Related Work • Post-Mapping Optimization (PMO) • Experimental Setup & Results • Conclusion**Experimental Setup & Results**• Setup • ABC environment • MiniSAT • Only able to add NAND • IWLS benchmark set originating from the OpenCores repository, which have already been synthesize, opimized, and mapped using a commercial synthesis tool • Intel Pentium 4 CPU with 3.4 GHz**Experimental Result I**• At least one level (d = 1) and at most two levels (D = 2) away from the target net. using 256 simulation slices (four words of size 64 bits, w = 4). SAT window b = 3**Conclusion**• In this paper, they outlined an efficient and effective optimization algorithm for mapped designs which leverages multiple ideas from technology-independent optimization such as SAT-sweeping and node addition and removal • The algorithm has moderate execution costs that increase roughly linear with the size of the circuit, allowing its use in industrial settings where circuits are very large