GPS Waypoint Navigation

1. GPS Waypoint Navigation Team M-2: Charles Norman (M2-1) Julio Segundo (M2-2) Nan Li (M2-3) Shanshan Ma (M2-4) Design Manager: Zack Menegakis Presentation 5: Top-Level Integration February 20, 2006 Overall Project Objective: Design a chip that navigates an aircraft to pre-determined waypoints.

2. Status • Design Proposal • Project chosen • Architecture Proposal • MATLAB simulated • Behavioral Verilog written & simulated • Floorplan • Structural Verilog written & simulated (except left side due to clock/buffer issues) • Accurate transistor count • Schematic Design • Schematic done, not tested completely • Layout • Simulations

3. Design Decisions • Accuracy • Latitude and longitude inputs in decimal format (6 decimal places) • GPS ~105 feet to 1 foot • Power • On/Off Power Control for Logic Modules • I/O pins • Reduced from >200 to 74 pins • Clock speed/buffers • Reduced 6 different clock speeds to 4 • All clock dividers depend on input clock to reduce delay • Transistor count went from 6,00012,0009,000 • Demux  Serial-Parallel Shift Register • Ripple carry adder   • Consume 60,000 times less static power than dynamic power at 1.8V • Added two invertors to comparators with carry outs to strengthen signal

4. Clock Speed • Input        –61.44 kHz for input        –Serial to parallel => 61.44kHz/30 = 2048Hz • Heading    –8Hz for registers before the heading calculation    –To observe changes in both longitude and latitude • 50 knots = 50*105 feet/min = 5250 feet/480 cyc ~ 11 feet/cyc –Gives accurate direction and speed • Output to Black box    –Parallel to serial => 8Hz *30 = 240hz

5. Clock Speed /* Clock converter from 61.44KHz to 2048Hz */ module inputclk (output clk, input clock,rst); wire [4:0] sum,num; reg5 r(num,sum,clock,rst,clk); add1_30 a1(sum,num); and (clk,num[4],num[3],num[2],num[1]); endmodule /* Clock converter from 61.44KHz to 240Hz */ module rclk (output clkr, input clock,rst); wire [7:0] sum,num; reg8 r(num,sum,clock,rst,clkr); add1_255 a(sum,num); and (clkr1,num[7],num[6],num[5]); and (clkr2,num[4],num[3],num[2]); and (clkr,clkr1,clkr2,num[1],num[0]); endmodule /* Clock converter from 61.44KHz to 8Hz*/ module outputclk (output clock8, input clock,rst); wire [12:0] sum,num; reg13 r(num,sum,clock,rst,clock8); add1_7680 a(sum,num); and (clock8,num[12],num[11],num[10],num[9]); endmodule /* Counter for Blackbox */ module counterr (output [29:0] ar, input clkr,clock,rst); wire [4:0] sum, numr; reset rcl(reset,clock,rst); reg5 r(numr,sum,clkr,reset,rest); add1_30 a(sum,numr); andnum an(ar,numr); and (rest,numr[4],numr[3],numr[2],numr[0]); endmodule module reset (output sto, input clock,rst); wire [8:0] sum,num; reg_9 r(num,sum,clock,rst,sto); add1_511 a(sum,num); and (clkr1,num[7],num[6],num[5]); and (clkr2,num[4],num[3],num[2]); and (st,clkr1,clkr2,num[1],num[0]); xor (sto,st,num[8]); endmodule

6. Serial - Parallel Shift Register

7. Ripple Carry Adder

8. Ripple Carry Adder

9. Overflow Case Problem : Flying over the border +180 to -180 Solution : if either longitude is negative and it’s close to the border, add 360 to the negative value

10. Block Level System Diagram

11. Transistor Estimates

12. SRAM

13. Problems • Over flow cases = transistor counts BOOM! • Clock delay causes problems… • Different reset times • fsm • sram • counter (Parallel-Serial to blackbox) • Transistor count

14. What’s Next… Here’s what’s on our agenda for next week… • Finish testing Schematics • Creating Module Layout

15. Questions?Comments?Ideas?