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Chapter 5

Chapter 5. Combinational Logic By Taweesak Reungpeerakul. Contents. Basic Combinational Logic Circuits Implement SOP and POS using Basic Logic Gates Universal Property of NAND and NOR Combinational Logic using NAND and NOR Operation with Pulse Waveforms Digital System Application. Inputs

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Chapter 5

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  1. Chapter 5 Combinational Logic By Taweesak Reungpeerakul 241-208 CH5

  2. Contents • Basic Combinational Logic Circuits • Implement SOP and POS using Basic Logic Gates • Universal Property of NAND and NOR • Combinational Logic using NAND and NOR • Operation with Pulse Waveforms • Digital System Application 241-208 CH5

  3. Inputs A B C AB AC BC OUT 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 1 1 0 0 1 1 1 0 0 0 0 0 0 1 0 1 0 1 0 1 1 1 0 1 0 0 1 1 1 1 1 1 1 1 5.1 Basic Combinational Logic Circuit Aims: Able to analyze&apply AND-OR,AND-OR-INV, XOR, XNOR circuits AB AC BC AB+AC+BC Actually AND-OR is a form of SOP expression ! 241-208 CH5

  4. AND-OR-INV Logic Invert AND-OR in SOP  AND-OR-INV in POS Prove ?? AB+AC+BC =(A+B)(A+C)(B+C) 241-208 CH5

  5. XOR OUT = AB + AB 241-208 CH5

  6. XNOR OUT = AB + AB = AB + AB 241-208 CH5

  7. Ex#1: OUT = ABC+DE Ex#2: OUT = A(BC+DE) 5.2 Implementing Combinational Logic Aims: Able to implement a logic circuit from a Boolean expression and truth table and also able to minimize logic circuit. 241-208 CH5

  8. From Truth Table Truth Table A B C OUT 0 0 0 0 0 0 1 1 0 1 0 1 0 1 1 0 1 0 0 0 1 0 1 1 1 1 0 0 1 1 1 0 If you should SOP form then just considering outputs “1s” 241-208 CH5

  9. Example TableLogic Circuit  Karnaugh Map  Simplified Circuit Truth Table A B C OUT 0 0 0 1 0 0 1 1 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 1 1 1 0 0 1 1 1 1 Minimize, don’t forget to use K-Map !! 241-208 CH5

  10. INV, OR, AND, and NOR created by using NAND gates 5.3 Universal Property of NAND&NOR Aims: implement OMV, OR, AND, and NOR using NAND or vice versa AND INV OR NOR 241-208 CH5

  11. INV, OR, AND, and NAND created by using NOR gates Universal Property of NOR AND INV OR NAND 241-208 CH5

  12. 5.4 Combinational Logic using NAND & NOR Aims: implement logic function using NAND/NOR gates • NAND; OUT = AB+CD = AB+CD= (AB)(CD) 241-208 CH5

  13. Dual Symbols of NAND, i.e. NAND+Negative-OR Always use the gate symbols in such a way that every connection between a gate output and a gate input is either bubble-to-bubble or nonbubble-to-nonbubble. AB+C ABC 241-208 CH5

  14. Example: implemented by NAND • Ex2: ABC+D+E • Ex1: ABC+DE 241-208 CH5

  15. Combinational Logic using NOR • NOR; (A+B)(C+D) = (A+B)(C+D)= (A+B)+(C+D) 241-208 CH5

  16. Dual Symbols (A+B)+C (A+B)C 241-208 CH5

  17. 5.5 Operation with Pulse Waveforms Aims: analyze combination logic circuits with pulse waveform inputs. develop a timing diagram for any given combination logic circuit with specified inputs Logic circuit  Timing diagram D C Determine the output waveform ? 241-208 CH5

  18. Develop logic circuit from waveforms Not in the form of NAND gates only yet ! Transform….. (use dual symbols) 241-208 CH5

  19. 5.6 Digital System Application MOTORS From switches 241-208 CH5

  20. Truth Table S1 S2 S3 S4 M1 M2 M3 M4 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 1 0 0 0 1 0 0 0 1 1 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 1 1 0 0 0 0 0 0 1 1 1 0 0 0 0 1 0 0 0 1 0 0 0 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 1 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 0 0 0 1 1 1 0 1 1 1 0 1 1 1 1 0 0 0 0 241-208 CH5

  21. Develop logic circuit from Truth Table 1 1 1 1 1 S1S4 For Motor M1 S1S2S3 241-208 CH5

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