Using Module Compiler to build FPGA Structures

1. Using Module Compiler to build FPGA Structures SeyiAyorinde ECE 6505

2. Outline • Architectures • FPGA • Look-Up Table (LUT) • Configurable Logic Block (CLB) • Switch Box • Using Module Compiler • Approach • Challenges

3. Architecture - FPGA http://chipdesignmag.com/images/articles/16/zeidman_figure2.gif

4. Architecture - LUTs

5. Architecture – CLB http://www.eecg.utoronto.ca/vpr/images/pl_ble_internals.jpg For the purposes of this project, 1 BLE = 1 CLB (no clustering)

6. Architecture – Connectivity to Interconnect http://www.eecg.toronto.edu/~vaughn/challenge/Fc.gif

7. Architecture – Switch Matrix http://www.eecg.toronto.edu/~vaughn/challenge/switch_box.gif

8. Project Architecture • 100 CLBs • 10 x 10 Array • 4-Input LUTs • No Clustering • Channel Width – 4 • Reconfigurable Switch – Mux

9. Mini-Example

10. Approach • Module Compiler – Relative Placement • Places portions of the design in specific areas relative to each other • Uses a grid of rows and columns • (0,0) is bottom left corner

11. Acronyms • HC and VC – Horizontal and Vertical Channels • SM – Switch Matrix • CLB – Configurable Logic Block

12. Relative Placement for FPGA

13. Relative Placement for FPGA

14. Approach • Code has been written to: • Create and place CLBs • Create and place HCs and VCs • Create and place SMs while connecting to HCs and VCs • Connect CLB Output to each channel • Connect CLB Input to each channel • Code needs to be written to: • Create and place I/O Blocks

15. Possible Issues • MCL Code • Demux function for connecting signal to multiple signals • If/else structure • Wire Directives (making sure vertical wires are vertical, etc.)

16. (Immediate) Future Work • Add I/O Blocks • Debug Code

17. Deliverables • MCL Code • Other MC Outputs • Layout file, Report Files, etc. • VHDL Code (Output of Module Compiler) • Schematic View • Layout (?) • Analysis of MC

18. Questions?