SOC FPGA Design Lab Discussion 5. SDR Lab Continued: DSP Blocks (Part I). Agenda. Discuss overall DSP architecture Channel selection filter Design CoreGen Implementation Discuss the tools which will be useful in development / verification of our design UDP streaming of data (as in Lab 4)
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SDR Lab Continued:
DSP Blocks (Part I)
43.75 +/- 3 MHz
25 Million 14-bit numbers / sec
48k samples / second
Given that we have sampled at 25MHz, the input to the signal processing blocks is depicted below
Graphics reprinted from : http://bruce.cs.tut.fi/invocom/p3-1/p3-1_2_1.htm
We are going to accomplish this tunable translation with a DDS for generation of a complex sinusoid, followed by a complex mixer. Details next week.
Ethernet to PC
Numint = int32(Num*32700+0.5);
How to choose?
Result is : impulse response of filter in a “coe” file, which we will use later when designing the filter. Note that filter gain has changed though over the unity gain filter we designed in Matlab. Now, signals in the passband will come out x32700 over the input level.
Overall, making the coefficients integers, (after multiplying by 32700) doesn’t affect our response too badly. With this scaling factor, our coefficient width is really only 9 bits. Some optimization between coefficient width and filter order could be undertaken if we chose.
As an example for high performance FPGA capabilities – consider Virtex 6.
DSP48E slices run up to 600MHz clock rates
Theoretical :172 GMACs / sec – 1.2 TMACs/sec
clk: IN std_logic;
nd: IN std_logic;
rfd: OUT std_logic;
rdy: OUT std_logic;
din: IN std_logic_VECTOR(15 downto 0);
dout: OUT std_logic_VECTOR(31 downto 0));
RDY : enable signal, result is present on rising edge of clock when this signal is high
ND : enable signal, new data is latched on rising edge of clock when this is high
Data is read out via JTAG cable
Essentially a logic analyzer inside the FPGA
FPGA resource limitedChipscope Pro
Example of Logic Analyzer view while system is running. Real data from target