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Chapter 9 Bipolar Logic Circuits. Microelectronic Circuit Design Richard C. Jaeger Travis N. Blalock. Chapter Goals. Bipolar switch circuits Emitter-coupled logic (ECL) Behavior of the bipolar transistor as a saturated switch Transistor-transistor logic (TTL)

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chapter 9 bipolar logic circuits

Chapter 9Bipolar Logic Circuits

Microelectronic Circuit Design

Richard C. JaegerTravis N. Blalock

Microelectronic Circuit Design

McGraw-Hill

chapter goals
Chapter Goals
  • Bipolar switch circuits
  • Emitter-coupled logic (ECL)
  • Behavior of the bipolar transistor as a saturated switch
  • Transistor-transistor logic (TTL)
  • Schottky clamping techniques for preventing saturation
  • Operation of the transistor in the inverse-active region
  • Voltage reference design
  • BiCMOS logic circuits

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the current switch emitter coupled pair
The Current Switch (Emitter-Coupled Pair)
  • The building block of emitter-coupled logic (ECL) is the current switch circuit which consists of matched components

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the current switch
The Current Switch
  • Depending on how much higher or lower the input voltage vI is compared to VREF, the reference current will switch to one of the legs creating a voltage vC1or vC2

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mathematical model for static behavior of the current switch
Mathematical Model for Static Behavior of the Current Switch
  • The previous figure showed the ideal case for switching the currents between the two legs, but in real BJTs current will be present in both legs depending upon vBE of each BJT in the pair
  • The collector current difference is given by:

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current switch analysis for v i v ref
Current Switch Analysis for vI > VREF
  • Given the circuit shown under the given bias conditions (vI is 300mV larger than VREF), the majority of current will flow in the left leg

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current switch analysis for v i v ref1
Current Switch Analysis for vI < VREF
  • Given the circuit shown under the given bias conditions (vI is 300mV less than VREF), the majority of current will flow in the right leg

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the emitter coupled logic ecl gate
The Emitter-Coupled Logic (ECL) Gate
  • The outputs of the previous current switch have the value of either 0V or –0.6V
  • The difference of the input and output of the current switch is exactly one base-emitter voltage drop
  • For a complete ECL gate, the voltages are shifted by a base-emitter drop as shown in the figure

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ecl gate summary
ECL Gate Summary

For vI = -0.7V

For vI = -1.3V

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ecl gate benefits
ECL Gate Benefits
  • ECL gates produce both true and complemented outputs
  • ECL gates are fast since it the BJTs are always in forward active mode, and it only takes a few tenths of a volt to get the output to change states, hence reducing the dynamic power
  • ECL gates provide near constant power supply current for all states thereby generating less noise from the other circuits connected to the supply

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noise margins for the ecl gate
Noise Margins for the ECL Gate

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current source implementation
Current Source Implementation
  • Instead of using actual current sources for the current biasing in an ECL gate, resistors can be used as shown below

Note that the currents in the emitter-follower legs will not be equal since the output voltages will be different. This will instead be looked at as an average value between the two legs.

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ecl gate design example
ECL Gate Design Example
  • Design an ECL gate with the circuit configuration shown on the previous slide to operate at a power supply of –3.3V knowing the following information

And a mean emitter follower current of 0.1mA

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ecl gate design example1
ECL Gate Design Example
  • For vI = –1.3V, Q1 will be off causing the common emitter voltage to be –1.7V. REE can now be calculated by the following:
  • And RC2 is:

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ecl gate design example2
ECL Gate Design Example
  • For vI = –0.7V, Q2 will be off causing the common emitter voltage to be –1.4V. IE1 can now be calculated by the following:
  • Now RC1 can be found as:

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ecl gate design example3
ECL Gate Design Example
  • Finally, R can be calculated by using the mean output voltage and current levels

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the ecl or nor gate
The ECL OR-NOR Gate

Three variations of a 3-input ECL OR-NOR Gate

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the emitter follower
The Emitter Follower
  • The main purpose of the emitter follower in ECL gates is to create a level shift in the output
  • The figure shows both the circuit and its transport model for the forward- active region

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the emitter follower1
The Emitter Follower
  • The emitter follower is called such since the voltage at the emitter follows the votlage at the base, but at an offset which can be seen in the ideal VTC

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the emitter follower with a resistor bias
The Emitter Follower with a Resistor Bias
  • As previously shown, the current source can be replaced with a resistor bias scheme
  • This technique will cause a change in vBE due to the variation of iE as vO changes, but this change is minimal and vO = vI – 0.7

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the emitter follower with a resistor load
The Emitter Follower with a Resistor Load
  • The addition of a resistive load will alter the minimum voltage of an ECL gate (when iE=0)

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emitter dotting or wired or logic
“Emitter Dotting” or “Wired-OR” Logic
  • The circuit shown in the figure exhibits two emitter followers in parallel with a common output
  • The result for the shown bias condition implies that Q2 is cutoff and Q1 has to handle 2IEE

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wired or logic function
Wired-OR Logic Function
  • The parallel emitter on the previous slide can be used to implement an OR function as shown in the figure, also called the Wired-OR
  • This is distinct to ECL logic since in most logic families, the outputs cannot be tied together

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design of reference voltage circuits
Design of Reference Voltage Circuits
  • So far the implementation of the VREF signal has not been discussed, but it can be created with a simple resistor voltage divider as seen below
  • The Thévenin equivalent circuit is used to show that the voltage at the base of Q2 will not be exactly 1V as designed due to the fact that there will be a resistive voltage drop across the Thévenin resistance induced by iB2

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temperature compensation
Temperature Compensation
  • Since the vBE of the BJT changes by approximately –1.8mV/K, it is obvious that when REE is used to replace the current switch current source, that iE2will vary with temperature
  • Two techniques are shown below that temperature compensate (track) the variation

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diodes in bipolar integrated circuits
Diodes in Bipolar Integrated Circuits
  • In ICs it is desired to have a diode match the base-emitter characteristics of a BJT (temperature compensation circuit)
  • Since a normal diode structure takes about the same amount of Silicon area as a BJT, it is just as easy to tie base to the collector (diode-connected) of a BJT to create a diode

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ecl power dissipation
ECL Power Dissipation
  • The static average power of an ECL inverter can be found by the following (referring to the shown circuit):

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power reduction
Power Reduction
  • Approximately 40% of the power is dissipated by the emitter-follower stages
  • One technique to reduce this current is to make the bias the emitter-follower resistors at a less negative value thereby reducing the current, however this requires an additional power supply
  • Another technique is to share the current in the manner shown on the next slide (similar to the wired-OR), however any output that is not driving another logic gate needs to be terminated with a resistor to the negative power rail

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power reduction1
Power Reduction

Changing the power supply

Repartitioned ECL gate

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gate delay
Gate Delay

ECL inverter with all capacitors shown

Simplified ECL gate model for dynamic response

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gate delay1
Gate Delay
  • The gate delays and voltages can be calculated with following expressions:

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power delay product
Power-Delay Product
  • The below figures illustrate the tradeoff of power and speed for ECL gates

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the saturating bipolar inverter
The Saturating Bipolar Inverter
  • One of the most basic circuits for BJT logic gates is the saturating bipolar inverter
  • The resistor pull the output high when vI is low, and the output goes to vCE when vI is high

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saturating bipolar inverter example
Saturating Bipolar Inverter Example
  • Design a saturating bipolar inverter such that the collector saturation voltage is 0.1V with a collector of 10A. Find the base current required to achieve these specs given the following:

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saturating bipolar inverter example1
Saturating Bipolar Inverter Example
  • First find the minimum VCE:
  • Next find Г:

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saturating bipolar inverter example2
Saturating Bipolar Inverter Example
  • Finally, solving for IB:

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load line visualization
Load Line Visualization
  • The following is a typical load line characteristic for a saturating bipolar inverter

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switching characteristics of the saturated bjt
Switching Characteristics of the Saturated BJT
  • An important switching factor is that when excess base current required to drive the BJT into saturation is stored into the base region. This charge needs to be removed before the BJT can be turned off.
  • This delay is called the storage time (tS)
  • The figures show typical switching characteristics

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switching characteristics of the saturated bjt1
Switching Characteristics of the Saturated BJT
  • The storage time delays can be calculated using the following expressions:
  • Where αF and αR are the forward and reverse common-base current gains, and τF and τR are the forward and reverse transit times

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a transistor transistor logic ttl prototype
A Transistor-Transistor Logic (TTL) Prototype
  • TTL has the workhorse for digital systems such as microprocessors for years
  • The basic structure for the TTL inverter is shown below

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ttl inverter operation
TTL Inverter Operation
  • The two figures show the bias points for the two standard low and high inputs
  • The output ranges from VOL = 0.15V to VOH = 5V

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power in the prototype ttl gate
Power in the Prototype TTL Gate
  • The power the TTL inverter dissipates for a low output is:
  • The power the TTL inverter dissipates for a low output is:

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v ih v il and noise margins for the ttl prototype
VIH, VIL, and Noise Margins for the TTL Prototype
  • The figure shows where VIL and VIH occur, and they can be approximated by the following expressions using standard TTL values:

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fanout limitations of the ttl prototype
Fanout Limitations of the TTL Prototype
  • For NMOS, CMOS, and ECL gates, fanout was not investigated in detail since the input current to these gates were considered to be zero. However, this is not the case for TTL as seen in the figure.

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fanout limitations of the ttl prototype example
Fanout Limitations of the TTL Prototype Example
  • For a TTL gate find:

a) the fanout limit (N) for a VCESAT2 less that 0.1V

b) the input current iIH and fanout limit for vI = vOH assuming βR1 = 2

Given the following:

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fanout limitations of the ttl prototype example1
Fanout Limitations of the TTL Prototype Example
  • First find N for vO = VL:
  • Next find the max iC:

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fanout limitations of the ttl prototype example2
Fanout Limitations of the TTL Prototype Example
  • Continuing:
  • The collector current can be no greater than
  • Which give the following:

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fanout limitations of the ttl prototype example3
Fanout Limitations of the TTL Prototype Example
  • But computing for vO = VH, it can be found the the fanout (N) is 7. Therefore, the max fanout for the circuit is 7
  • Part b) analysis - Finding iIH and N with βR1 = 2

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the standard 7400 series ttl inverter
The Standard 7400 Series TTL Inverter
  • One problem of the TTL inverter prototype described so far is that the dynamic response is asymmetrical due to the use of a resistive load to pull the output up and a BJT to pull the output down
  • Another problem is that the fanout capability is highly sensitive to βR

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the standard 7400 series ttl inverter1
The Standard 7400 Series TTL Inverter
  • The classic approach to fixing these problems is the implementation of the 7404 hex inverters in a dual-in-line package (DIP)

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the standard 7400 series ttl inverter2
The Standard 7400 Series TTL Inverter
  • In the 7404 TTL inverter circuit, Q4 replaces the passive resistive load pull-up in the prototype TTL inverter to make it an active pull-up circuit
  • Q3 and D1 ensure that the Q4 is turned off when Q2 is on

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output analysis of the 7404 inverter
Output Analysis of the 7404 Inverter

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power consumption of the 7404
Power Consumption of the 7404

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ttl propagation delay and power delay product
TTL Propagation Delay and Power Delay Product
  • The analysis of propagation delay for TTL gates is difficult due to the number of transistors involved, so the results can be approximated through simulation as shown

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ttl vtc and noise margins
TTL VTC and Noise Margins
  • The figure shows the VTC simulation results of the TTL inverter
  • Using the results from the simulation the noise marigns can be calculates as

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fanout limitations of standard ttl
Fanout Limitations of Standard TTL
  • The active pull drastically improves the fanout capabilities of the TTL inverter
  • However, due to process variations, and the requirement for the device to operate over a range of temperatures, N is specified to be less than 10

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logic functions in ttl
Logic Functions in TTL
  • The basic structure for the TTL NAND gate:

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ttl nand gates
TTL NAND Gates
  • The parallel input can be applied to create multiple input NAND gates as seen in the complete circuit schematic for the 7410 three-input NAND gate

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ttl nand gates1
TTL NAND Gates
  • One good thing about the multiple input NAND gate is that it can use a merged transistor structure to save silicon area since the input BJTs share their emitters and collectors

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other ttl gates
Other TTL Gates

TTL AND-OR-Invert

Low-power TTL NAND gate

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input clamping diodes for ttl
Input Clamping Diodes for TTL
  • From a transient simulation of the TTL inverter, a negative-going transient can be observed due to the fast input signal transition
  • Another source of the transients is from the distributed L-C interconnection network between gates causing “ringing”

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input clamping diodes for ttl1
Input Clamping Diodes for TTL
  • To suppress these transient effects, diodes can be placed at the input to clamp the signal to ground

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schottky clamped ttl
Schottky-Clamped TTL
  • Since the saturated transistors in TTL gates substantially slows down the dynamic response of the logic gates, the Schottky-clamped transistor can be used to help this problem
  • The Schottky diode keeps the BJT from going into deep saturation

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schottky clamped ttl inverter prototype
Schottky-Clamped TTL Inverter Prototype
  • Replacing the two BJTs with Schottky-clamped transistors, the Schottky TTL inverter can be formed

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three input schottky ttl nand gate
Three-Input Schottky TTL NAND Gate
  • Each saturating transistor is replaced be a Schottky-clamped transistor
  • Q6, R2, and R6 replaces RE in the original version which eliminates the first “knee” voltage thereby making the transition region narrower
  • Q5 eliminates the need for D1 by providing extra drive to Q4

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low power schottky ttl
Low-Power Schottky TTL

Advanced low-power Schottky TTL

Low-power Schottky TTL

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ecl and ttl pdp comparison
ECL and TTL PDP Comparison

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bicmos logic
BiCMOS Logic
  • BiCMOS is a complex processing technology that provides both NMOS and PMOS, as well as npn and pnp bipolars
  • The high impedance input of logic gates (does not require much to drive them) are provided from the MOSFETs and high current drive can be provided from the BJTs due to their high current gain and transconductance

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bicmos buffers
BiCMOS Buffers
  • The CMOS inverter only has to supply enough current to drive the bases of the BJTs in the BiCMOS buffer
  • The BJT stage can then be designed to drive the capacitive load at a certain speed

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bicmos buffers1
BiCMOS Buffers
  • The BiCMOS buffers in the figures present two method to restore the full logic swing at the output

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binmos buffer
BiNMOS Buffer
  • In some BiCMOS processes, a good npn might be provided, but a sub-par pnp is available, which could put limitations on your design
  • A buffer can be implemented in the manner shown in the figure using only npn bipolars

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other binmos circuits
Other BiNMOS Circuits

Full-swing BiNMOS inverting buffers

BiNMOS buffer using a single npn bipolar

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bicmos logic gate
BiCMOS Logic Gate
  • More complex logic gates can also be implemented using BiCMOS design

Two-input BiCMOS NOR gate

Two-input BiNMOS NOR gate

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end of chapter 9
End of Chapter 9

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