WP6: Interconnect Technology and Quality Assurance

1. WP6: Interconnect Technology and Quality Assurance Michael Campbell and Alan Honma

2. QA and reliability testing lab status (1) Personnel: • 20% physicist (A. Honma) 2008 → 30% 2009 • Fulltime proj. assoc. (Florentina Manolescu) starting Nov. 2008 • 20% technician (Ian McGill) starting Nov. 2008 • maybe a student or fellow from mid-2009? Alan Honma

3. QA and reliability testing lab status (2) Equipment: 1) Stress screening (T and RH cycling) chamber - ESPEC Thermotec type EGNX12-6CWL– quotations requested, purchase soon. 2) Shear test cartridge for pull tester – for bond and chip shear strength measurements 3) Digital SLR, microscope C-mount, adjustable table stand - for photo documentation 4) Extreme temperature range thermo/hygrometer w/remote probe 5) PC + monitor + printer for DAQ and general usage (to be ordered) If sufficient 2008 funds: 6) Vibration tester – researching requirements, purchase by end of 2008 Alan Honma

4. QA and reliability testing lab status (3) Activities planned: • Accelerated life test of uncleaned soldering on high current carrying PCBs (in progress). • Studies of anomalous behaviour in silicon strip sensors as a function of humidity and temperature. • Finding optimum thermal cycling parameters for detector modules and components. • Creation of a QA and reliability reference website for HEP silicon sensors and modules. • Creation of a “library” of problems and solutions found in past and existing HEP silicon sensors and modules. Alan Honma

5. Present status of bump bonding (1/2) • Typically bump bonding is done by electroplating both the UBM and solder through the same photoresist mask. • Electroplating is an old and well characterised process technology. With electroplating it is possible to deposit sub 20 µm bumps with 40 µm pitch with relatively good uniformity. • Most of the factors that restrict the resolution of electroplating are related to wet-etching of the seed metal layers for electrodeposition. If wet-etching can be avoided, finer pitches are may be used. Bumping process flow using electroplating – a single mask process. Sami Vaehaenen

6. Present status of bump bonding (2/2) • Sub 10 µm bumps with very fine pitches could be realized with evaporation/sputtering and lift-off techniques, but it is time consuming and expensive process. • Difficult process which requires strict control and understanding (process temperatures, air humidity, etc.), it’s not suitable for production without an excellent process. • Solder ball bumping (SBB) or Au stud bumping (e.g. placing individual bumps/studs with modified wire bonder) is not a choice for high-density area array bump matrix, because parallel deposition of bumps is faster and cheaper. • However, solder ball bumping could replace wire bonding in 3D packaging used with through silicon vias (TSV). • Actually, SBB is one of the cheapest bumping methods for solutions with low I/O’s. • Solder bump flip chip has proven to be reliable interconnection technology for ultra-fine-pitch (UFP) radiation detectors. Sami Vaehaenen

7. Present status of flip chip bonding • High accuracy flip chip bonding has proven to be slow. • Combination of high-accuracy bonding, precise levelling and high force to be seems to be a difficult equation for equipment manufacturers. • Bonding rate of commercial electronics with coarse pitches is about 10 s/placement. In demanding pixel detector applications the bonding rate has shown to be ~10 min/placement  there is room for development work. • Status of new flip chip bonding equipment should be reviewed to speed up the average bonding rate. • Unfortunately, there seems to be only one equipment manufacturer which has dedicated their systems for high-accuracy bonding for large area chips (S.E.T , former Suss Microtec). Sami Vaehaenen

8. Cost distribution of bump and flip-chip bonding • Bump bonding costs of a single detector unit has been over 200 €. • Here’s an estimation how the costs have been shared between readout chip (ROC) bumping, sensor chip (SC) bumping and flip chip bonding. • Readout chips are cheapest because they are typically single chips on big (8”) wafers  many good chips from each bumped wafer. • Sensor bumping is the dominating cost-issue at the moment. Use of ladder shaped sensor chips (e.g. multiple ROC’s placed on single sensor unit) makes the situation even worse due to higher material loss (bumping yield). Sami Vaehaenen

9. Yield considerations • Building of a detector consist of many steps, which all have their individual yields. • Readout chips • Chip design, minimum line width used, chip area dependent yield factors, probing yield (chips can be detroyed), bumping yield, thinning yield (+ thickness dependency), handling yield, visual inspection accuracy. • Sensor chips • Manufacturer’s sensor yield (not 100%), bumping yield, handling yield, chip geometry, dicing yield, visual inspection accuracy. • Assembled detector chips • Flip chip yield, testing, handling and mounting yields on PCB’s. • Overall manufacturing yield of detectors can be affected if there’s motivation for it! Sami Vaehaenen

10. Case1: ALICE vs. NA60 sensor layouts Theoretical calculation based on existing projects • ALICE and NA60 projects have been using similar ROC’s, but the sensor chips have had different shapes. • ALICE ladder has a large sensor substrate on which 5 ROC’s are bonded. NA60 project uses single sensor chips. Theorethical calculation • In typical case, at least one ladder will be lost during bumping process, because the yield isn’t 100% (red cell). This will have a significant effect on process yields  requires a lot of extra work! • If the sensor wafer is cracked, all ladders will be typically lost. In case of single chips some of the singles might be saved. Sami Vaehaenen

11. Bumping summary “+” signs mean strengths and “-” weaknesses. Electroplating rankings are over-pessimistic, because in reality the UBM Ni is deposited in sequence with the solder. Sami Vaehaenen

12. Flip chip bonding summary ACF – Anisotropic conductive Film ACA – Anisotropic Conductive Adhesive ICA – Isotropic Conductive Adhesive Btech ACF – ACF with aligned Ni fibres Z- bond – ACF with curing under magnetic field US bond – ultrasonic bonding Sami Vaehaenen

13. 3D - Introduction • Masking costs for very deep sub-micron CMOS are rising strongly with each new generation • Interconnect begins to limit processing power • Some applications require interconnect between different technologies • 3D becomes a hot topic in academia and industry

14. 3D basics • Processes are usually defined as wafer to wafer, chip to wafer or chip to chip. • Wafer to wafer requires identical wafer sizes and (usually) identical wafer types. A typical example is memory chip stacking. • Main advantage: many chips connected at once • Main disadvantage: process yield if no built-in redundancy • Chip to wafer allows different technologies to be connected. Example sensor electronics for automotive applications • Main advantage: Known Good Die are preselected • Main disadvantage: takes more time per assembly • Chip to chip has been used for HEP pixel detectors. Note that solder bump bonding is a means of 3D interconnect • Main advantage: known process • Main disadvantage. Costly manipulation of individual die

15. 3D Basics (contd) • There are 2 main process families: Via first and Via last • Bonding can be face to face, face to back or back to back • Choice may depend on the interconnect density needed and the number of layers needed

16. (Wafer) Bonding Choices Fermilab experience Electrical and Mechanical Bonds (MIT LL) (RTI) (Tezzaron) (Ziptronix) Ray Yarema, TWEPP 2008 TWEPP-08

17. 3D suppliers (incomplete list) • Europe • IZM (via last, SLID interconnect, solder bumps) • IMEC (via last, Cu-Sn-Cu interconnect, In bumps) • VTT (via last, solder bumps) • US • Tezzaron + Chartered (Singapore) (Fastack - via first) • RTI (via last, Cu-Cu and Cu-Sn-Cu interconnect) • Ziptronix (Direct Bond Interconnect) • Lincoln Labs (via first, SOI) • Allvia (via last) • Japan • OKI (SOI) • Zycube

18. 3D projects in HEP • Atlas (MPI/IZM) • Exploring via last option (Inter Chip Vias) with vias drilled from wafer front side. 4-side buttable tiles • SLIC (Solid Liquid Interdiffusion) Cu-Sn-Cu interconnect for thin sensors and readouts • VIP chips for ILC (Fermilab/Lincoln Labs) • 3D in house process • 1st attempt at 3D in HEP community • Issues with yield and SOI transistors • Fermilab MPW with Tezzaron-Chartered • Many designs to be implemented on the same run • Possibility of sensor bumping with Ziptronix • Participants mainly in MAPS community

19. Miscellaneous personal thoughts • 3D has clear advantages for MAPS. • 3D could have big advantages for XFEL/ILC-like machines. Need to ‘save’ 3000 frames quickly before slow readout • Do SLHC pixels need 3D? 4-side buttable thin tiles would be great • Likely challenges: • How to segment and manage design • Intimate link between layers (risk of X-talk) • Cooling! • How good are the MAPS sensors after 3D processing? • Only one sizable vendor (at present) • Planarity issues for new bumping processes

21. Summary • QA and reliability testing • Full time project associate (F. Manolescu) started 1 Nov • High performance ESPEC Thermotec type EGNX12-6CWL climatic chamber has been selected and is being procured • Other small equipment is in place, more to be procured soon • Work has (just) started on QA web site and database • Lab location currently under discussion: shared - bondlab/reliability testing /silicon R&D facility - being developed • Interconnect Technologies • Fellow (S. Vaehaenen) started on 1st September • First report on the cost drivers for present day bump bonding has been presented • Possible solutions for lower cost bumping have been identified for various sensor/readout pitches • The 3D ‘landscape’ has been surveyed and contacts with the LHC experiments initiated