RISC Reduced Instruction Set Computer - PowerPoint PPT Presentation

RISCReduced Instruction Set Computer

Presentation by:

Joe Ziems

Sesin Johnson

Kyungmi Ku

Zoya Izralevich

• RISC stands for Reduced Instruction Set Computer.
• The instruction set is the hardware language

that tells the processor what to do.

• The main alternative to RISC is CISC, which stands for Complex Instruction Set Computer.
• Both RISC and CISC are design approaches to microprocessors.
• CISC is the older approach, and came about to maximize the performance of earlier computers, where instructions were executed sequentially. This sequential execution only allowed one instruction to execute at a time. CISC enhanced on this combining the sequential instructions into a single instruction reducing the amount of time retrieving instruction from memory.

• RISC approach developed as a result of developments occurring in the 1970s, like increase in memory size with a decrease in cost, advanced compilers, and high speed caches.
• All started with 3 research projects
• IBM 801, Berkeley RISC, Stanford MIPS
• In late 1970s, IBM was the first to start
• In 1980, David A. Patterson of Berkeley, began the project that gave this new approach its name, RISC
• A year later, Stanford MIPS was developed
• The future of RISC is bright!!!
• Performance increase of 55% per year!!!

• Characteristics of RISC:
• Simplified instructions, most taking only one clock cycle.
• Few addressing modes, since most all instructions use register-to-register operations, register addressing.
• A large number of general purpose registers.
• Pipelining - fetching a next instruction while a previous instruction executes.
• Pre-fetching & Speculative execution – processor guesses whether a condition will be met from a branch condition.
• Fixed address length instructions
• Floating Point Units, FPUs

• Developed in 1991 by MIPS Technology, Inc.
• Stands for Microprocessor without Interlocked Pipeline Stages
• 94 Instructions, 4 byte instruction size
• Uses 64 bits for all internal and external data paths, registers, and ALU
• 32 general-purpose 64 bit registers
• One addressing mode (two for optimized embedded systems)

• 64 bit chip divided into two parts, CPU and memory management unit
• CPU operates on simple instructions and addresses
• Memory management unit is more complex to permit complex virtual memory schemes
• Thirty-two 64 bit registers, 128 KB on-chip cache (half for data, half for instructions)
• No condition codes, instead any such codes are stored in registers for explicit use by later instructions

• Stands for Scalable Processor Architecture
• SPARC Architecture, formulated at Sun Microsystems in 1985
• Developed in 1987
• 69 Instructions, 4 byte instruction size
• 1 Addressing mode
• Uses register windows
• 40-520 general-purpose registers

• SPARC is “scalable”
• Register stack can be expanded to reduce loads and saves between functions
• Can also be scaled down to reduce interrupt or context switch time
• Function calls are more frequent, so larger register set is usually a better solution

69 Instructions

32 bit bus

Uses register windows

1 addressing mode

40-520 general purpose registers

32KB cache

MIPS R4000

94 Instructions

64 bit bus

Does not use register windows

1 addressing mode (2 for optimized embedded systems)

32 general purpose registers

128KB cache

• MIPS R4000 is a good option for embedded systems, such as PDA’s, cell phones, hand-held game devices
• SPARC is an excellent option for servers
• SPARC is more developer friendly
• With SPARC having more general purpose registers, the access time is quicker
• Thanks for your attention.
• Any questions?