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On-Chip Context Save and Restore of Hardware Tasks on Partially Reconfigurable FPGAs

On-Chip Context Save and Restore of Hardware Tasks on Partially Reconfigurable FPGAs. Aurelio Morales-Villanueva and Ann Gordon-Ross + Department of Electrical and Computer Engineering University of Florida, Gainesville, Florida, USA.

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On-Chip Context Save and Restore of Hardware Tasks on Partially Reconfigurable FPGAs

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  1. On-Chip Context Save and Restore of Hardware Tasks on Partially Reconfigurable FPGAs Aurelio Morales-Villanueva and Ann Gordon-Ross+ Department of Electrical and Computer Engineering University of Florida, Gainesville, Florida, USA + Also Affiliated with NSF Center for High-Performance Reconfigurable Computing This work was supported by National Science Foundation (NSF) grants EEC-0642422 and IIP-1161022, and Programa de Ciencia y Tecnología (FINCyT) under contract 121-2009-FINCyT-BDE

  2. Motivations • Partially reconfigurable (PR) FPGAs enhance hardware multitasking of shared resources • Hardware tasks (PR modules (PRMs)) share PR regions (PRRs) • Only reconfigured PRR halts execution • PRM preemption: savesPRM’sexecutionstate (i.e., context) • PRM resumption: restores previous PRM’s saved context • Prior works only provide partial solutions Contributions • On-chip context save and restore (CSR) software • Application/systemindependent (i.e., portable) • On-chip CSR software benefits • No external/custom hardware required for operation • No tool flow changesrequired • Autonomuous • Maximizes task throughput, no re-execution time for PRM upon resumption

  3. Context save (TCS) execution time Results Context restore (TCR) execution time • All execution times show linear growth rate • Facilitates predictability of CSR times for different PRR sizes • On-chip CSR software benefits for system designers • Portability across different FPGA architectures • Allows to trade off PRR size and CSR times based on application requirements

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