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FIIT STU 2004/05 VNORENÉ SYSTÉMY

Procesory a architektúry pre VS VLIW ASIPs. FIIT STU 2004/05 VNORENÉ SYSTÉMY. Benedikt Nagy. Obsah. Úvod do ASIPs VLIW ASIPs Point of view: HW vs. SW Metódy optimalizácie z hľadiska SW. Záver. Úvod do ASIPs.

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FIIT STU 2004/05 VNORENÉ SYSTÉMY

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  1. Procesory a architektúry pre VS VLIW ASIPs FIIT STU 2004/05VNORENÉ SYSTÉMY Benedikt Nagy

  2. Obsah • Úvod do ASIPs • VLIW ASIPs • Point of view: HW vs. SW • Metódy optimalizácie z hľadiska SW • Záver

  3. Úvod do ASIPs • Pojmy: VLIW, ASIP, datapath, dataflow, paralelizmus, súbor registrov, funkčná jednotka • Použitie ASIPs • Z čoho sa skladá? • Aké spôsoby návrhu sa používajú?

  4. Úvod do ASIPs • Z čoho sa skladá ASIP

  5. VLIW ASIPs • Pohľady na problematiku optimalizácie • Hardvér: počet a typy FU, usporiadanie FU a RF, usporiadanie pamäti • Softvér: snaha o paralelizmus

  6. Metódy optimalizácie • Binding – dataflow na datapath

  7. Metódy optimalizácie • Retiming -> + výkon; - pamäťová kapacita r1[1]=r2[-1]*c1; for i=1 to n-1{ r1[i+1]=r2[i-1]*c1; r2[i]=r1[i]+c2;} r2[n]=r1[n]+c2; for i=1 to n { r1[i]=r2[i-2]*c1; r2[i]=r1[i]+c2; }

  8. Metódy optimalizácie • Scheduling – zrušenie nenulových hrán

  9. Záver • Dosiahnutý výsledok • Ďalšie špecifiká metód

  10. Použité zdroje • 1. Jacome, M., De Veciana, G., Akturan, C. – Resource constrained dataflow retiming heuristics for VLIW ASIPs • 2. Jacome, M., De Veciana, G.– Design Challenges for New Application-Specific Processors • 3. Jacome, M., De Veciana, G.– Lower Bound on Latency for clustered VLIW Datapaths • 4. Lapinskii,V., Jacome, M., De Veciana, G.– Cluster Assignment for High-Performance Embedded VLIW Processors • 5. Lapinskii,V., Jacome, M., De Veciana, G. – HighQuality Operation Binding for Clustered VLIW Datapaths • 6. Schlett, M. – Trends in embedded mikroprocessors design. • 7. Middha, B., Raj, V., Gangwar, A. - A Trimaran Based Framework for Exploring the Design Space of VLIW ASIPs with Coarse Grain Functional Units • 8. Kayhan, K., - An ASIP Design Methodology for Embedded Systems • 9. Akturan,C., Jacome, M. - FDRA: A Software-Pipelining Algorithm for Embedded VLIW Processors • 10. Gschwind, M. - Instruction Set Selection for ASIP Design

  11. Ďakujem za pozornosť Koniec

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