Design of a Simple Customizable Microprocessor

1. Design of a Simple Customizable Microprocessor • SIMP – A Simple Customizable Microprocessor* - Cont’d • SIMP Implementation – Datapath + Control Unit • Datapath consists of all registers + interconnect structures (such as Muxes) and ALU etc. • Control Unit provides proper timing, sequencing, and synchronization of micro-operations, other activation signals + control signals for external world * Chapter 7 and 15, “Digital System Design and Prototyping” Fig-05: Basic Partition of SIMP Design Introduction to ASIC Design

2. Design of a Simple Customizable Microprocessor • SIMP Implementation – Cont’d • Datapath Implementation • PC Module/Block module PC(q, lda, ldd, inc, clr, clk, pca, pcd); output [11:0] q; input [11:0] pca, pcd; input lda, ldd, inc, clr, clk;  reg [11:0] q;  always @(posedge clk or negedge clr) begin  if (!clr) q <= 12'd0; else begin if (lda) q <= pca; else if (ldd) q <= pcd; else if (inc) q <= q + 1; else q <= q; end end endmodule * Chapter 7 and 15, “Digital System Design and Prototyping” Fig-06: Program Counter Block Introduction to ASIC Design

3. Design of a Simple Customizable Microprocessor • SIMP Implementation – Cont’d • Datapath Implementation – Cont’d • SP Block module SP (q, d, dec, inc, init, clk); output [11:0] q; input [11:0] d; input dec, inc, init, clk; reg [11:0] q; always @(posedge clk or posedge init) begin if (init) q <= 12'hff0; else if (dec) q <= q - 1; else if (inc) q<= q + 1; else q <= q; end endmodule * Chapter 7 and 15, “Digital System Design and Prototyping” Fig-07: Stack Pointer Block Introduction to ASIC Design

4. Design of a Simple Customizable Microprocessor • SIMP Implementation – Cont’d • Datapath Implementation – Cont’d • Working Register B module regb(q, d, ld, dec, inc, clr, com, clk); output [15:0] q; input [15:0] d; input ld, inc, dec, clr, com, clk; reg [15:0] q; always @(posedge clk) begin if (ld) q <= d; else if (inc) q <= d + 1; else if (dec) q <= d - 1; else if (com) q <= ~q; else q <= q; end endmodule * Chapter 7 and 15, “Digital System Design and Prototyping” Fig-08: Working Register B Introduction to ASIC Design

5. Design of a Simple Customizable Microprocessor • SIMP Implementation – Cont’d • Datapath Implementation – Cont’d • Arithmetic Logic Unit (ALU) module alu(z, q, cout, a, b, cin, als); output [15:0] q; output cout; output z; input [15:0] a; input [15:0] b; input cin; input [1:0] als; reg [15:0] q; reg cout; assign z = (q == 16'd0); always @(a or b or als or cin) begin case (als) 2'b00: {cout, q} = a + b + cin; 2'b01: q = a & b; 2'b10: q = a; 2'b11: q = b; default: q = a; endcase end endmodule * Chapter 7 and 15, “Digital System Design and Prototyping” Introduction to ASIC Design

6. Design of a Simple Customizable Microprocessor • SIMP Implementation – Cont’d • Datapath Implementation – Cont’d • Data Bus Multiplexer module dbusmux(out, pcdata, tempdata, aludata, din, dbus_sel); output [15:0] out;input [15:0] aludata, din; input [11:0] pcdata, tempdata; input [1:0] dbus_sel;reg [15:0] out;  always @(dbus_sel or aludata or din or pcdata or tempdata) begin case (dbus_sel) 2'b00: out = {4'd0, pcdata}; 2'b01: out = {4'd0, tempdata}; 2'b10: out = aludata; 2'b11: out = din; default: out = din; endcase end endmodule * Chapter 7 and 15, “Digital System Design and Prototyping” Fig-09: Data Bus Multiplexer Introduction to ASIC Design

7. Design of a Simple Customizable Microprocessor • SIMP Implementation – Cont’d • Datapath Implementation – Cont’d • Datapath Overall * Chapter 7 and 15, “Digital System Design and Prototyping” Fig-10: Datapath Integrated all Together Introduction to ASIC Design