interrupts on the intel 8051 l.
Skip this Video
Download Presentation
Interrupts on the Intel 8051

Loading in 2 Seconds...

play fullscreen
1 / 10

Interrupts on the Intel 8051 - PowerPoint PPT Presentation

  • Uploaded on

Interrupts on the Intel 8051. Presented by: Joe Conner For: Advanced Embedded Systems Design BAE 5030 08/30/04. Overview. Memory Map Interrupts How interrupts are handled Response Time. Memory Map. TCON (0x88 ). IE (0xA8). IP (0xB8). SCON (0x98). Interrupts.

I am the owner, or an agent authorized to act on behalf of the owner, of the copyrighted work described.
Download Presentation

PowerPoint Slideshow about 'Interrupts on the Intel 8051' - arnon

Download Now An Image/Link below is provided (as is) to download presentation

Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author.While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server.

- - - - - - - - - - - - - - - - - - - - - - - - - - E N D - - - - - - - - - - - - - - - - - - - - - - - - - -
Presentation Transcript
interrupts on the intel 8051
Interrupts on the Intel 8051
  • Presented by: Joe Conner
  • For: Advanced Embedded Systems DesignBAE 5030
  • 08/30/04
  • Memory Map
  • Interrupts
  • How interrupts are handled
  • Response Time
memory map
Memory Map
  • TCON (0x88)
  • IE (0xA8)
  • IP (0xB8)
  • SCON (0x98)
  • The 8051 provides 5 interrupt sources
    • INT0
    • INT1
    • TF0
    • TF1
    • RI/TI

External Interrupts and can be either level or transition activated

Timer 0 and 1 overflow/rollover activated

Serial Port both receive and transmit

Since both TX and RX are the same interrupt, the service routine will have to determine which it was.

All the bits that generate interrupts can be set or cleared by software, with the same results as if they had been set or cleared by hardware.

interrupts enabled and disabled
InterruptsEnabled and Disabled
  • All interrupt sources can be individually enabled or disabled by setting bits in Special Function Register IE
how interrupts are handled
How Interrupts are Handled
  • Interrupts flags are sample at S5P2 of every machine cycle.
  • The 8051 then generates a call (LCALL) to the corresponding interrupt service routine provided one of the following conditions is NOT meet.
    • An interrupt of equal or higher priority is already in progress
    • The current instruction is not yet complete
    • The instruction in progress is RETI or any write to the IE or IP registers
how interrupts are handled8
How Interrupts are Handled
  • Priority can be set by the software
  • All interrupts can either be set to a high or low priority
  • Priority works as follows
    • High-priority interrupts can not be interrupted
    • Low-priority interrupts can be interrupted ONLY by high-priority interrupts
    • If two request of different priorities occur ‘simultaneously’, the request with the higher priority is serviced.
    • If request with the same priority occur ‘simultaneously’, then an internal polling sequence is used
how interrupts are handled9
How Interrupts are Handled
  • If none of the previous conditions have violated, then the 8051 will generate a LCALL to the appropriate serving routine. In most cases it also clears the flag that generated the interrupt.
    • Note: Serial Port flag is never cleared and as such must be handled by software
  • LCALL pushes the current contents of the Program Counter onto the stack and reloads an address that depends on the source of the interrupt
  • Execution proceeds until RETI is encountered. The execution of this command allows the 8051 to know that the current interrupt routine is no longer in progress
  • The 8051 then reloads the Program Counter from the stack and continues from where is left off.
response time
Response Time
  • In a single-interrupt system, the response time is always more then 3 cycles, but less then 9 cycles.