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ESA EJSM/JGO Radio & Plasma Wave Instrument (RPWI) Prag meeting 100218 Lennart Åhlén

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ESA EJSM/JGO Radio & Plasma Wave Instrument (RPWI) Prag meeting 100218 Lennart Åhlén - PowerPoint PPT Presentation


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ESA EJSM/JGO Radio & Plasma Wave Instrument (RPWI) Prag meeting 100218 Lennart Åhlén. Plasma waves. Electric fields Plasma measurements Conductivities. B. Radio. Main box mechanics . Backplane with power distribution, analog and digital interfaces Board size: 20x15cm TBC

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slide2
Plasma waves

Electric fields

Plasma measurements

Conductivities

B

Radio

slide3
Main box mechanics
  • Backplane with power distribution, analog and digital interfaces
  • Board size: 20x15cm TBC
  • Connectors: Micro-D type
  • Box : 21x16x12 cm average 4.7mm wall thickness for Al.
  • Distance between Boards: 20mm
slide4
Power
  • Voltages:
  • +3.3V Digital interface supply
  • +1.8V Digital DPU and FPGA core supply
  • +-8V Analog
  • Software current limiters (msec turn off at latch up)
  • Common ground for all voltages
  • Only one ground in the backplane
  • Total power: 6.6W average 10W peak (100ms)

Instrument interfaces

  • Digital: Differential
  • Analog: Single ended (TBC)

Satellite interfaces

  • 2 Mbit SpaceWire
  • Single ended (TBC)
slide5
Radiation protection
  • Spot shielding should be used for all S/C external electronics
  • Box and spot shielding should be used for the RPWI Box
  • Use of Rad Hard components
  • Box shielding 4.7mm
  • 1.1 kg extra mass needed for 8mm box protection
  • 3kg allocated by ESA for radiation shielding of RPWI
  • Action:
  • Calculations of internal box radiation levels using GEANT 4
slide12
WHY Should we use the ESA ASICs ?
  • They are guarantied Rad hard
  • ESA will do the paper work
  • ESA will pay for the qualification
  • We will save mass (up to 650g)
  • We may save power that can be used for signal processing
  • We may save money
  • We can convert saved mass into antenna length
  • If they are not delivered in time we blame ESA for the delay
slide14
LP_PWI Preamplifier
  • Specifications:
  • Switchable E-field / Density
  • 100mW power consumption
  • 500kRad Radiation hardend
  • Positive feed back current generator
  • E-field:
  • DC-300Hz +-100V input range
  • DC to 3MHz small signal bandwidth
  • Better than 10^12 input resistance
  • 1nA – 100nA Current Bias range
  • 16 nV/sqr(Hz) noise
  • Density:
  • DC to 10kHz bandwidth
  • 10pA to 100uA input current range
  • +-100V Voltage Bias range

New development: Find new low noise Rad hard operational amplifiers

Develop a MEMS chip including nano-switches and amplifiers

MEMS amplifier 10x10x1mm total mass 4x30g (4x250g)

slide15
RA_PWI and RWI Preamplifier

FET follower or FET input negative feed back amplifier ?

  • High distortion
  • Limited output range
  • Low power
  • Simple
  • Low distortion
  • Medium power
  • Complex

Specifications:

1kHz to 50MHz Bandwidth 2 nV/sqr(Hz) noise

+-1V input range 100mW power consumption

Amplifier from Tohoku University 100Hz to 50MHz 0.6W

slide16
RPWI Grounding block diagram

EMC Actions.

Define acceptable satellite RE and CE levels for the

frequency range DC to 45 MHz.

MIL-STD-462D ECSS-E-ST-20-07C(31July2008)

slide17
Develop the RPWI EMC requirements for the S/C by interaction during S/C design

Experimenter EMC requirements

  • All spacecraft surfaces exposed to the plasma environment shall be sufficiently conductive and grounded. < 5 kohm/sq
  • Small surfaces differential charging potential shall not exceed +-10 V, assuming a plasma current of 5 nA/cm2
  • The S/C structure shall not be used as return path for power and signals except for sensor signals to avoid common impedance coupling and magnetic disturbances.
  • Isolated receivers and balanced differential signals should be used as subsystem signal interfaces.
  • All active wires shall be twisted with its return wire and loops on circuit boards should be minimize to reduce magnetic disturbances.
  • The spacecraft system shall use a Distributed Single Point Grounding.
  • Secondary power shall be grounded to structure only once in each unit / experiment.
  • Cable shields shall be grounded to structure ground at both ends. Shields shall not be used as the return path for signal or power.
  • Non-magnetic materials shall be used wherever possible.The use of ferro-magnetics shall be avoided wherever possible.
  • It is recommended to use crystal oscillator controlled DC/DC converters
low voltage power supply lvps
Low Voltage Power Supply (LVPS)

Göran Olsson

Royal Institute of Technology (KTH)

Space and Plasma Physics

slide19
LVPS IN RPWI JGO

LFA + AM

+8V / -8V

3.3V

1.8V

LVPS-A

SCM

+8V / -8V

3.3V

SCM PREAMP

1.8V

+8V

3.3V

DPU

-8V

1.8V

3.3V

CEB BACKPLANE

LVPS CONTROL & MONITORING

1.8V

LP-PWI

+8V / -8V

3.3V

LP-PWI Preamps

1.8V

LVPS-B TBD

+8V / -8V

RWI RA-PWI HFA

3.3V

RWI Preamps

1.8V

RA-PWI Preamp

Clock, Control, Data and Emergency Power-Off, A + B

slide20
LVPS Requirements
  • Functional:
  • DC power to all RPWI instruments:
    • ±8V +3.3V, +1.8 V from 25-36 V input, nominal total power output: ~10 W
  • CEB Form Fit:
    • PCB Dimensions 200x 150 x 1.6 mm
    • Component height 12 mm upper side, 3 mm lower side
    • Backplane connector 160 pin, 3 row Airborn WG series
    • Mass 300 g
  • Primary to secondary isolation
  • Temperature range: -30 °C to +50 °C operating
  • Redundant DC/DC converters and digital controllers TBD
  • Power Switching: 5 instruments having two to four supply voltages
  • Voltage and Current Monitoring
  • Overcurrent Tripping; Limits under software control
  • Temperature Monitoring: DC/DC converter and SCM sensor
  • Performance:
  • No-load Power (Including DC/DC converter, controller, monitoring and switches): 1.1 W
  • Differential Efficiency: 82%
  • Output Deviation: ±5% from nominal including all effects
  • Output Ripple: < 5 mVrms
slide21
LVPS Block Diagram

From

SC

28V

DC/DC Converter A

1.8, 3.3 V

Voltage

And

Current

Monitors

(4)

CEB

BPLN

DPU

Common-Mode

Filter

DC/DC Converter B

1.8, 3.3 V

From

SC

28V

Common-Mode

Filter

Power

Switches

(9

Instruments)

Voltage

and

Current

Monitors

(24)

1.8, 3.3, ±8 V

Common Bus

  • Redundant TBD DC/DC Converters and Controllers chained with the DPU
  • Unused chain is a cold spare
  • Common power bus for all instruments. Design to minimize risk of single point failures here.
  • What if both chain A and B are powered? Must be survivable, but no functional requirement. - No mutual interlock implemented. Subject of further study.
  • 1.8 V is regulated to 1.5 V locally on each subsystem
  • Power switches have turn-on ramping
  • Emergency Power-Off

Housekeeping

From SCM Thermistor

Controller A

FPGA

CDPU-A Ctrl: Clock, Command, Data, EPO

Controller B

FPGA

slide22
DC/DC Converter A/B

Primary

Shielded

Secondary

Shielded

Main Transformer

Input: 27- 36 V

First Stage

Second Stage

Outputs:

+1.8 V, 1.1 A

+3.3 V, 1.1 A

+8 V, 350 mA

-8 V, 300 mA

Pulse-Width Modulator ‘Forward’ Converter

420 kHz

EMI Filter

Synchronous Rectifiers

13-14 V DC

  • Inrush current limiter

Output Filters

Transformer Driver

-

Switchmode Regulator Controller

50mΩ

+

Internal: ±15 V

  • Regulated input voltage to Transformer Driver
  • Current positive feedback: Counterbalances losses in driver transistors, transformer and rectifiers.
  • Primary to Secondary Isolation
  • Double Shielding
  • Push-Pull
  • Full-Wave
  • 210 kHz
  • Full-Wave Rectification
  • LC Pi Filters
  • No Feedback from Secondary

Two-stage Conversion:

Excellent input and load regulation

Low noise

Low output cross-regulation

Slightly lower efficiency

slide23
Digital Controller A/B

Power Switch Control (9)

FPGA

3.3 V

Linear Regulators:

1.5 V

2.5 V

HK Control (ADC, Mux, Gain Switch)

DC/DC A/B

  • Instrument Power Control
  • Housekeeping Control with Storage and Readout
  • Overcurrent Tripping, limits under software control
  • IVM: Actel ProASIC3 A3P250
  • FM: Actel RTSX72

LVDS

CDPU A/B

Housekeeping ADC Data

  • System clock derived from the CDPU interface clock: 1.048 MHz
  • If three consecutive samples (~15 ms) exceed the limit ► All voltages turned off for the affected instrument
slide24
Design Heritage
  • DC/DC Converter, Housekeeping System and Stepper Motor Controller for EMMA, a plasma payload on the Swedish Astrid-2 satellite, launched December 10, 1998. Dimensions 177 x 134 x 16 mm. DC/DC design power 10 W. COTS components. This design has many features in common with the MMS LVPS.
  • DC/DC Converter for SPEDE, a plasma payload on the SMART-1 ESA Lunar Orbiter, launched 2003. Dimensions 71 x 44 x 11 mm. Design power is a mere 1.2 W.

Impacted on the Moon as planned on September 3, 2006.

LVPS IVM on the UNH lab bench with co-delivered dummy load board

slide26
Low and high frequency analyzers

Lennart Åhlen

Scientists dream receiver

A downgrade is needed for the JGO receivers.

tda development of fpga algorithms for digital analyzers to obtain high dynamic measurement range
TDA: Development of FPGA algorithms for digital analyzers to obtain high dynamic measurement range

JGO Scientists dream receiver

A downgrade is needed for the JGO receivers.

Dynamic range: The ratio of the specified maximum signal level capability of a system to its noise level in a record of continues sampled data.

What is required to fulfill the JGO since objective?

Questions to be answered by the RPWI scientists.

Ranges and overlap for the low and high frequency receivers?

Wave-form capture?

Low and High frequency data coverage?

Number of parallel data channels?

Type of on-board data analyzes?

slide28
Low frequency receiver
  • Signal processing: FFT, I/Q, Filter bank, Wavelets, PFT,
  • Buffer memory for wave form capture and Burst data.
  • Dynamic range: 80dB to ~120dB @ 100Hz bandwidth

High frequency receiver

  • Burst data signal processing: FFT, I/Q, Filter bank, Wavelets, PFT,
  • Buffer memory for wave form capture and Burst data.
  • Dynamic range: 70dB to ~100dB @ 10kHz bandwidth
  • Measurement range: 70dB to ~120dB @ 10kHz bandwidth
  • Dynamic range: 70dB to ~100dB @ 10kHz bandwidth
slide29
Under sampling high frequency receiver
  • All high speed ADCs has a higher analog bandwidth than the maximum sampling rate.
  • This makes it possible to build HF digital receivers by use of under-sampling.
  • Under-sampling design approach is replacing mixer-based heterodyne receivers.
  • Signal processing: FFT, I/Q, Filter bank, Wavelets, PFT,

Principle of under sampling

slide30
Dual 1 0 -1 I/Q Mixer including SH
  • Conventional mixer using high speed analog switches.

Antenna impedance measurements

  • Net work analyzer S11 type measurements
  • Impedance antenna to plasma vs. frequency
  • Useful for side-by-side antenna comparisons
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