WP3 Microelectronics and interconnection technology

1. WP3 Microelectronics and interconnection technology Hans-Günther Moser - MPI Valerio Re - INFN AIDA meeting with National Contacts, April21, 2010

2. WP3 Tasks Task 1. Coordination and Communication • To coordinate and schedule the execution of the WP tasks • To monitor the work progress and inform the project management and the participants within the WP • To follow-up the WP resource utilization • To prepare the internal and Deliverable Reports Task 2. 3D Interconnection • Creation and coordination of a framework to make 3D interconnection technology available for HEP detectors • Organisation of dedicated fabrication of sensors and electronics optimized for 3D interconnection • Construction of demonstrator detectors using 3D technology to access this technology Task 3. Shareable IP Blocks for HEP • Creation and coordination of a framework for the design of low and medium complexity microelectronics libraries and blocks in advanced submicron technologies to be made available to the community of users in HEP • Organization of the design and qualification of a set of blocks using selected and qualified technologies • Distribution and documentation of the library of functional blocks • Organisation of regular Microelectronics Users Group meetings to exchange information, plan and coordinate actions related to the creation of a shared library of macro blocks.

3. WP3 participants Task 2 (3D interconnection): • Participants: AGH-UST, CERN, CEA, CNRS (CPPM and IPHC), CSIC (UB), INFN, DESY (MPG-MPP and UBONN), STFC, SWEDET • Associates: IPASCR, NTUA (DEMOKRITOS), UNIGLA, UNILIV, FOM Task 3 (Shareable IP blocksfor HEP): • Participants: AGH-UST, CEA, CERN, CNRS • (LAL and LPNHE) • Associates: INFN-MI, INFN-PV and DESY (UBONN)

4. WP3 Budget Our proposal is to comply with the new reduced budget mostly by cutting the costs of a CMOS MPW run in Task 3.2. A consensus was reached on using AIDA money to cover only the costs of access to the full extra wafers needed for the 3D interconnection process. These extra wafers will be fabricated in MPW runs that are already planned and funded.

5. Old Budget: task 2 (3D interconnection) Weagreedto concentrate on ASIC–sensor interconnection with TSV forbacksideconnectivity(4-side buttablesensors). Weagreedto cut the CERN budget for a CMOS MPW from 200 kEuroto 100 KEuro. Thiswill finance only the overheadconnectedto the full wafer access (extra wafers).

6. Task 2 (3D interconnection) • There are severalfundedprojectsoutside AIDA thatalreadyplanfor CMOS MPW runs (IBM, Chartered, Tezzaron,…). WP3 particpants are alreadytaking part in theseruns. Itwasagreedthatthese MPW runswillbemadeavailabletofabricatewafersfor the 3D interconnection withsensors in the AIDA project. These MPW runswill include readoutcircuitswith a layout compatiblewith 3D integration. • Weagreedto concentrate on onesupplierfor the 3D processing. We’lldefinecriteriafor the selection (price, experience, flexibility). • We’llalsoneedtoselect a (1, maybe 2) sensorsupplier(ifpossible, “edgeless” sensors). Wecould profit from ATLAS and CMS runs (planar, 3D pixels). Special processing steps are neededfor 3D integration.

7. Old Budget: Task3 (Shareable IP Blocks) • EC fundingcoversmanpowerfordeveloping and maintaining IP blocks • Weagreedtopreservethis task, with minor cuts (30 kEuro)

8. Backup slides

9. Task2: 3D interconnection • Complex technology, high development costs, both in personnel and materials resources  very difficult for an individual laboratory to achieve the ultimate goals • Within this task a network activity is set up to fully assess the technology in a collective effort around common demonstrators. Thinning, etching of the TSV and vertical interconnection: Europe has a limited number of microelectronics research centres which are capable of providing such services. This work package will work with vertical integration providers to assess 3D interconnection processes, build an infrastructure for 3D post-processing and make them accessible to the community for the development of high performance pixel sensors. MPW runs with full wafer access: Complete wafers are needed for most of the post processing steps which are necessary for TSV. A solution is to bundle designs from different HEP labs to fill a complete wafer in an engineering run. The owners agree (NDA) to use only the chips they own. Such a run could be organized by an institution like CERN, who has already good contacts to industry. Sensor production optimized for 3D integration: Standard silicon sensors are not necessarily suited for 3D applications. The interconnection technology may have special requirements on planarity and needs special barrier and metal layers (structured) for the interconnection. These requirements need either to be implemented in the manufacturer’s technology or the sensors need to be post processed by a third party. Further R&D is needed to reduce the inactive edge area to make better use of 3D possibilities (‘slim edge’ or ‘active edge’ sensors)

10. Task 3: Shareable IPs for HEP • This task, which includes the definition, design and qualification of an initial set of blocks, is naturally related to Task 2, which provides the underlying silicon technologies. • Blocks that are already identified as being essential for facilitating different designs are numerous in both in the analog domain (band-gap references, biasing digital to analog converters, voltage regulators) and in the digital domain (PLLs, IO radiation tolerant pads, parametrizablerad-tolerant memory blocks, SEU resistant storage elements for digital libraries). • The task will coordinate the definition, design, validation, distribution and documentation of the blocks to be designed across a number of collaborating Institutes which will maintain the long term responsibility of supporting users who choose to use one or more of these blocks in their projects • Candidate technologies: CMOS 130 nm and 90 nm, SiGe 130 nmBiCMOS