lecture 29 ieee 1149 1 jtag advanced boundary scan description language bsdl n.
Download
Skip this Video
Loading SlideShow in 5 Seconds..
Lecture 29 IEEE 1149.1 JTAG Advanced Boundary Scan & Description Language (BSDL) PowerPoint Presentation
Download Presentation
Lecture 29 IEEE 1149.1 JTAG Advanced Boundary Scan & Description Language (BSDL)

Loading in 2 Seconds...

play fullscreen
1 / 21

Lecture 29 IEEE 1149.1 JTAG Advanced Boundary Scan & Description Language (BSDL) - PowerPoint PPT Presentation


  • 408 Views
  • Uploaded on

Lecture 29 IEEE 1149.1 JTAG Advanced Boundary Scan & Description Language (BSDL). Special scan cells and pins Cell timing / wiring constraints Cell delay measurements Boundary Scan Description Language Summary. Observe-Only Scan Cell. Control & Observe Scan Cell. Bidirectional Pins.

loader
I am the owner, or an agent authorized to act on behalf of the owner, of the copyrighted work described.
capcha
Download Presentation

PowerPoint Slideshow about 'Lecture 29 IEEE 1149.1 JTAG Advanced Boundary Scan & Description Language (BSDL)' - arella


Download Now An Image/Link below is provided (as is) to download presentation

Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author.While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server.


- - - - - - - - - - - - - - - - - - - - - - - - - - E N D - - - - - - - - - - - - - - - - - - - - - - - - - -
Presentation Transcript
lecture 29 ieee 1149 1 jtag advanced boundary scan description language bsdl
Lecture 29 IEEE 1149.1 JTAGAdvanced Boundary Scan & Description Language (BSDL)
  • Special scan cells and pins
  • Cell timing / wiring constraints
  • Cell delay measurements
  • Boundary Scan Description Language
  • Summary

VLSI Test: Bushnell-Agrawal/Lecture 29

observe only scan cell
Observe-Only Scan Cell

VLSI Test: Bushnell-Agrawal/Lecture 29

control observe scan cell
Control & Observe Scan Cell

VLSI Test: Bushnell-Agrawal/Lecture 29

bidirectional pins
Bidirectional Pins

VLSI Test: Bushnell-Agrawal/Lecture 29

one pin control of multiple tri state pins
One-Pin Control of Multiple Tri-State Pins

VLSI Test: Bushnell-Agrawal/Lecture 29

illegal cell use
Illegal Cell Use

VLSI Test: Bushnell-Agrawal/Lecture 29

data non inversion requirement
Data Non-Inversion Requirement

VLSI Test: Bushnell-Agrawal/Lecture 29

system data non inversion
System Data Non-Inversion

VLSI Test: Bushnell-Agrawal/Lecture 29

cell delay constraints
Cell Delay Constraints
  • Delay between falling TCK edge and changes at component output pins may be skewed
    • May need to avoid simultaneous output switching to save power or avoid burnout
  • Scan register cells with latched parallel outputs
    • May be reset to either logic 0 or 1
      • When Test-Logic-Reset TAP controller state entered
      • On first falling TCK edge in Test-Logic-Reset state

VLSI Test: Bushnell-Agrawal/Lecture 29

setup and hold time delay measurement
Setup and Hold Time Delay Measurement

VLSI Test: Bushnell-Agrawal/Lecture 29

propagation delay measurement method
Propagation Delay Measurement Method

VLSI Test: Bushnell-Agrawal/Lecture 29

board level bus test
Board Level Bus Test

VLSI Test: Bushnell-Agrawal/Lecture 29

circuit with testing burnout problem
Circuit with Testing Burnout Problem

VLSI Test: Bushnell-Agrawal/Lecture 29

purpose of boundary scan description language bsdl
Purpose of Boundary Scan Description Language (BSDL)
  • Facilitate communication of information describing test logic of parts:
    • Between companies and CAD tools
    • Used by automatic test-pattern generators
    • Used by synthesis tools to synthesize test logic
  • Not usable as a simulation model
  • Cannot describe voltages, currents, or timing
  • Implemented as subset of VHDL
    • Must modify for certain VHDL tools

VLSI Test: Bushnell-Agrawal/Lecture 29

features describable in bsdl
Features Describable in BSDL
  • Describable:
    • Length & structure of boundary scan reg.
    • Availability of optional TRST pin
    • Physical locations of TAP pins
    • Instruction codes
    • Device identification code
  • Not describable:
    • TAP controller state diagram
    • Bypass register
    • Length of Device Identification Register
    • Presence of SAMPLE / PRELOAD, BYPASS, EXTEST instructions
    • Operation of user-defined instructions

VLSI Test: Bushnell-Agrawal/Lecture 29

bsdl description components
BSDL Description Components
  • Entity description -- component-specific test logic parameters
  • Standard VHDL package & package body
    • Defines BSDL subset of VHDL
    • Defines commonly used boundary scan cell types
  • User-specified VHDL packages & package bodies

VLSI Test: Bushnell-Agrawal/Lecture 29

bsdl example
BSDL Example

entity diff is

generic (Physical_Pin_Map: string:= “Pack”);

port ( TDI, TMS, TCK: in bit;

TDO: out bit; IN1, IN2: in bit;

OUT1: out bit; OUT2: buffer bit;

OUT3: out bit_vector (1 to 8);

OUT4: out bit_vector (4 downto 1);

BIDIR1, BIDIR2, BIDIR3: inout bit;

GND, VCC: linkage bit);

use STD_1194_1_1994.all;

attribute BOUNDARY_REGISTER of diff:entity is ...

VLSI Test: Bushnell-Agrawal/Lecture 29

pin descriptions
Pin Descriptions
  • Standard USE statement (required):

use STD_1149_1_1994.all;

  • PIN Types:
    • in (input-only)
    • out (may be tri-state or open-collector)
    • buffer (active, 2-state, always driven)
    • inout (bidirectional)
    • linkage (power, ground, analog, non-connect)
  • Relate logical signals to package physical pins
  • Group ports -- differential voltage or current pairs (one signal is always complement of other)

VLSI Test: Bushnell-Agrawal/Lecture 29

tap descriptions
TAP Descriptions
  • Says which logical signals comprise the TAP
  • Specify which input port logic values enable JTAG compliance (part can either conform to JTAG or refuse to conform)
  • Instruction register description:
    • Length
    • Op Codes -- can add optional instructions
    • Mapping from bit patterns to instruction Op Codes
    • Define private instructions
    • Specify bit pattern captured in Capture-IR controller state (2 LSB’s are always “01”)
  • IDCODE and USERCODE register contents

VLSI Test: Bushnell-Agrawal/Lecture 29

scan cell definitions
Scan Cell Definitions
  • Define existence and length of boundary scan register cells -- have these types:
    • INPUT -- control & observe, observe-only
    • CLOCK -- cell at clock input
    • OUTPUT2 -- drives 2-state output
    • OUTPUT3 -- drivers 3-state output
    • CONTROL -- controls 3-state output
    • CONTROLR -- disabled in Test-Logic-Reset state
    • INTERNAL -- not associated with digital pin
    • BIDIR -- reversible cell for bidirectional pin
    • OBSERVE_ONLY -- single input observe-only cell
  • Define which instructions access which registers

VLSI Test: Bushnell-Agrawal/Lecture 29

summary
Summary
  • Boundary Scan Standard has become absolutely essential --
    • No longer possible to test printed circuit boards with bed-of-nails tester
    • Not possible to test multi-chip modules at all without it
    • Supports BIST, external testing with Automatic Test Equipment, and boundary scan chain reconfiguration as BIST pattern generator and response compacter
    • Now getting widespread usage

VLSI Test: Bushnell-Agrawal/Lecture 29