1 / 50

BalsaOpt a tool for Balsa Synthesis

Francisco Fernández-Nogueira, UPC (Spain) Josep Carmona, UPC (Spain). BalsaOpt a tool for Balsa Synthesis. Contents. Logic Synthesis into the Balsa flow Design flow Structural methods to fight the state explosion Structural Clustering based on Petri nets composition Experimental Results.

amena
Download Presentation

BalsaOpt a tool for Balsa Synthesis

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. Francisco Fernández-Nogueira, UPC (Spain) Josep Carmona, UPC (Spain) BalsaOpt a tool for Balsa Synthesis

  2. Contents • Logic Synthesis into the Balsa flow • Design flow • Structural methods to fight the state explosion • Structural Clustering based on Petri nets composition • Experimental Results

  3. Logic Synthesisinto the Balsa System

  4. Design flow Cluster HCs

  5. Design flow ; | | | | Describe Behavior

  6. ; | | | | Design flow ; | | | | Compose STGs

  7. Design flow Hide Internals

  8. Design flow State Explosion Problem STATE GRAPH PETRI NET Enumerate States

  9. Contents • Logic Synthesis into the Balsa flow • Design flow • Structural methods to fight the state explosion • Structural Clustering based on Petri nets composition • Experimental Results

  10. Structural Methods MILP formulation: MILP “s=0 implicit” MILP “s=1 implicit” #(σ1,s+) = #(σ1,s-) + 1 #(σ2,s-) = #(σ2,s+) + 1 M0[s=0] + M0[s=1] = 1 Solve CSC (Moebius [Carmona et al. 2006])

  11. Structural Methods Project into Signal Support (Moebius [Carmona et al. 2006]) + Delete Dummies

  12. Structural Methods PETRI NET STATE GRAPH Enumerate States

  13. Structural Methods LOGIC EQUATION (ack_16) ack_16 = csc_2' csc_3' csc_1' Synthesize (Petrify [Cortadella et al. 1996])

  14. Contents • Logic Synthesis into the Balsa flow • Design flow • Structural methods to fight the state explosion • Structural Clustering based on Petri nets composition • Experimental Results

  15. Clustering Techniques Cluster HCs

  16. Clustering Techniques Cluster HCs

  17. Clustering Techniques Complex STG Describe Behavior

  18. Structural Clustering Techniques • Well-structured Petri net subclasses: State machine (SM), Marked Graph (MG), Free-choice (FC) and Asymmetric choice (AC) • Idea: well-structured STGs will be obtained if the growth of cluster is bounded by one of these subclasses

  19. Structural Clustering Techniques PN Class of Synchronization Area

  20. Structural Clustering Techniques PN Class of HC Connection

  21. Clustering Techniques Cluster HCs

  22. Clustering Techniques Cluster HCs

  23. Clustering Techniques Describe Behavior

  24. Experimental Results

  25. Conclusions Balsa [Edwards et al. 2002] + Moebius [Carmona et al. 2006] Structural Clustering Techniques + Petrify [Cortadella et al. 1996] + To Avoid complex STGs Structural Clustering Techniques [Fernández-Nogueira et al. 2008] To Fulfill Structural Properties Safe Logic Synthesis Logic Synthesis into the Balsa System

  26. Conclusions • The design of async circuits cannot be faced without the help of CAD tools. • This work is an example where the theory of Petri nets helps for optimizing async circuits. Advocate for interdisciplinary research. • Future Work: • Other optimization goals: energy consumption. • Specification of more HCs • Paper at PATMOS’08

  27. Are There Any Questions? Thank You!

  28. Logic Synthesis of async controllers Solve CSC (Petrify [Cortadella et al. 1996])

  29. + Structural Methods Project into Signal Support (Moebius [Carmona et al. 2006])

  30. + Structural Methods State Explosion Problem Enumerate States

  31. + Structural Methods State Explosion Problem Enumerate States

  32. + Structural Methods Project into Signal Support (Moebius [Carmona et al. 2006]) + Delete Dummies

  33. TRASH SLIDES

  34. ... Introduction: asynchronous clock ... Asynchronous Advantages: D1 D2 DN in out ... • A Good Match with Heterogeneous System Timing t1 t2 tN-1 • High Performance • Low Power Dissipation • Low Noise and • Low Electromagnetic Emission C1 C2 CN ... L1 L2 LN in out ... t1 t2 tN-1

  35. Structural Methods MILP formulation: MILP “s=0 implicit” MILP “s=1 implicit” #(σ1,s+) = #(σ1,s-) + 1 #(σ2,s-) = #(σ2,s+) + 1 M0[s=0] + M0[s=1] = 1 Solve CSC (Moebius [Carmona et al. 2006])

  36. Related Work Signal Transition Graphs State Based Methods Tangram+Assassin [Kolks et al. 1996] Assassin [Ykman-Couvreur et al. 1994] Petrify [Cortadella et al. 1996] Unfolding Methods Tangram+Petrify [Peña et al. 1996] CLP [Khomenko et al. 2002] CSAT [Khomenko et al. 2003] Structural Methods Moebius [Carmona et al. 2006] Balsa+Minimalist [Chelcea et al. 2002] DesiJ [Schaefer & Vogler. 2007] Burst-mode Finite-state Machines Minimalist [Fuhrer et al. 1999] Balsa+Moebius+Petrify [Fernández-Nogueira et al. 2008] Handshake Components Tangram [van Berkel et al. 1999] Balsa [Edwards et al. 2002]

  37. Introduction Moore's Law System on a Chip

  38. Design flow Delete Dummies

  39. Structural Clustering Techniques Synchronization Area

  40. Structural Clustering Techniques PN Class of Synchronization Area

  41. Introduction “As it becomes impossible tomove signal across a largedie within one clock cycle,the likely result is a shift toasynchronous design style”. International TechnologyRoadmap for Semiconductors (ITRS 2001) Intel Pentium IV (47M transistors)

  42. Summary of problems for shifting to asynchronous • Asynchronous circuits are difficult to design, need for CAD tools. • Most of the dominant CAD tools for asynchronous synthesis suffer from the state explosion problem. • If asynchronous HDLs are used, the derived circuits are unoptimized, in terms of area and speed.

  43. Contents • Introduction • Synthesis of async circuits • VLSI programming • Logic synthesis • Logic Synthesis into the Balsa flow • Design flow • Structural methods to fight the state explosion • Structural Clustering based on Petri nets composition • Experimental Results

  44. ro li * x FF not x lo ri Each circle mapped to a netlist Asynchronous Hardware Description Languages (a?byte & b!byte) begin x0: var byte | forever do a?x0 ; b!x0 od end a b Buffer passive port active port ; a b T x T Data path

  45. Asynchronous Hardware Description Languages Balsa [Edwards et al. 2002] procedure buffer2 (input i1,i2 : byte; output o1,o2 : byte;) is variable x1,x2 : byte; begin loop i1 -> x1 || i2 -> x2 ; o1 <- x1 || o2 <- x2 end end Syntax-directed Translation

  46. Contents • Introduction • Synthesis of async circuits • VLSI programming • Logic synthesis • Logic Synthesis into the Balsa flow • Design flow • Structural methods to fight the state explosion • Structural Clustering based on Petri nets composition • Experimental Results

  47. Bus Data Transceiver Device D DSr VME Bus Controller LDS DSw LDTACK DTACK Logic Synthesis of async controllers PETRI NET Describe Behavior

  48. Logic Synthesis of async controllers Complete State Coding Conflicts PETRI NET STATE GRAPH Enumerate States

  49. Logic Synthesis of async controllers Solve CSC (Petrify [Cortadella et al. 1996])

  50. Logic Synthesis of async controllers LOGIC EQUATIONS lds = csc0 + d d = ldtackcsc0 dtack = d csc0 = dsr (csc0 + ldtack') Synthesize (Petrify [Cortadella et al. 1996])

More Related