BalsaOpt a tool for Balsa Synthesis

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# BalsaOpt a tool for Balsa Synthesis - PowerPoint PPT Presentation

Francisco Fernández-Nogueira, UPC (Spain) Josep Carmona, UPC (Spain). BalsaOpt a tool for Balsa Synthesis. Contents. Logic Synthesis into the Balsa flow Design flow Structural methods to fight the state explosion Structural Clustering based on Petri nets composition Experimental Results.

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## BalsaOpt a tool for Balsa Synthesis

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Presentation Transcript
Contents
• Logic Synthesis into the Balsa flow
• Design flow
• Structural methods to fight the state explosion
• Structural Clustering based on Petri nets composition
• Experimental Results
Design flow

Cluster HCs

Design flow

;

| |

| |

Describe Behavior

;

| |

| |

Design flow

;

| |

| |

Compose STGs

Design flow

Hide Internals

Design flow

State Explosion Problem

STATE GRAPH

PETRI NET

Enumerate States

Contents
• Logic Synthesis into the Balsa flow
• Design flow
• Structural methods to fight the state explosion
• Structural Clustering based on Petri nets composition
• Experimental Results
Structural Methods

MILP formulation:

MILP “s=0 implicit”

MILP “s=1 implicit”

#(σ1,s+) = #(σ1,s-) + 1

#(σ2,s-) = #(σ2,s+) + 1

M0[s=0] + M0[s=1] = 1

Solve CSC (Moebius [Carmona et al. 2006])

Structural Methods

Project into Signal Support (Moebius [Carmona et al. 2006]) + Delete Dummies

Structural Methods

PETRI NET

STATE GRAPH

Enumerate States

Structural Methods

LOGIC EQUATION (ack_16)

ack_16 = csc_2' csc_3' csc_1'

Synthesize (Petrify [Cortadella et al. 1996])

Contents
• Logic Synthesis into the Balsa flow
• Design flow
• Structural methods to fight the state explosion
• Structural Clustering based on Petri nets composition
• Experimental Results
Clustering Techniques

Complex STG

Describe Behavior

Structural Clustering Techniques
• Well-structured Petri net subclasses: State machine (SM), Marked Graph (MG), Free-choice (FC) and Asymmetric choice (AC)
• Idea: well-structured STGs will be obtained if the growth of cluster is bounded by one of these subclasses
Structural Clustering Techniques

PN Class of Synchronization Area

Structural Clustering Techniques

PN Class of HC Connection

Clustering Techniques

Describe Behavior

Conclusions

Balsa [Edwards et al. 2002]

+

Moebius [Carmona et al. 2006]

Structural Clustering Techniques

+

+

To Avoid complex STGs

Structural Clustering Techniques

[Fernández-Nogueira et al. 2008]

To Fulfill Structural Properties

Safe Logic Synthesis

Logic Synthesis

into the Balsa System

Conclusions
• The design of async circuits cannot be faced without the help of CAD tools.
• This work is an example where the theory of Petri nets helps for optimizing async circuits. Advocate for interdisciplinary research.
• Future Work:
• Other optimization goals: energy consumption.
• Specification of more HCs
• Paper at PATMOS’08
Logic Synthesis of async controllers

Solve CSC (Petrify [Cortadella et al. 1996])

+ Structural Methods

Project into Signal Support (Moebius [Carmona et al. 2006])

+ Structural Methods

State Explosion Problem

Enumerate States

+ Structural Methods

State Explosion Problem

Enumerate States

+ Structural Methods

Project into Signal Support (Moebius [Carmona et al. 2006]) + Delete Dummies

...

Introduction: asynchronous

clock

...

D1

D2

DN

in

out

...

• A Good Match with Heterogeneous System Timing

t1

t2

tN-1

• High Performance
• Low Power Dissipation
• Low Noise and
• Low Electromagnetic Emission

C1

C2

CN

...

L1

L2

LN

in

out

...

t1

t2

tN-1

Structural Methods

MILP formulation:

MILP “s=0 implicit”

MILP “s=1 implicit”

#(σ1,s+) = #(σ1,s-) + 1

#(σ2,s-) = #(σ2,s+) + 1

M0[s=0] + M0[s=1] = 1

Solve CSC (Moebius [Carmona et al. 2006])

Related Work

Signal Transition Graphs

State Based Methods

Tangram+Assassin

[Kolks et al. 1996]

Assassin [Ykman-Couvreur et al. 1994]

Unfolding Methods

Tangram+Petrify

[Peña et al. 1996]

CLP [Khomenko et al. 2002]

CSAT [Khomenko et al. 2003]

Structural Methods

Moebius [Carmona et al. 2006]

Balsa+Minimalist

[Chelcea et al. 2002]

DesiJ [Schaefer & Vogler. 2007]

Burst-mode Finite-state Machines

Minimalist [Fuhrer et al. 1999]

Balsa+Moebius+Petrify

[Fernández-Nogueira et al. 2008]

Handshake Components

Tangram [van Berkel et al. 1999]

Balsa [Edwards et al. 2002]

Introduction

Moore's Law

System on a Chip

Design flow

Delete Dummies

Structural Clustering Techniques

PN Class of Synchronization Area

Introduction

“As it becomes impossible tomove signal across a largedie within one clock cycle,the likely result is a shift toasynchronous design style”.

(ITRS 2001)

Intel Pentium IV (47M transistors)

Summary of problems for shifting to asynchronous
• Asynchronous circuits are difficult to design, need for CAD tools.
• Most of the dominant CAD tools for asynchronous synthesis suffer from the state explosion problem.
• If asynchronous HDLs are used, the derived circuits are unoptimized, in terms of area and speed.
Contents
• Introduction
• Synthesis of async circuits
• VLSI programming
• Logic synthesis
• Logic Synthesis into the Balsa flow
• Design flow
• Structural methods to fight the state explosion
• Structural Clustering based on Petri nets composition
• Experimental Results

ro

li

*

x

FF

not x

lo

ri

Each circle mapped to a netlist

Asynchronous Hardware Description Languages

(a?byte & b!byte)

begin

x0: var byte

| forever do

a?x0 ; b!x0

od

end

a

b

Buffer

passive port

active port

;

a

b

T

x

T

Data path

Asynchronous Hardware Description Languages

Balsa [Edwards et al. 2002]

procedure buffer2 (input i1,i2 : byte; output o1,o2 : byte;) is

variable x1,x2 : byte;

begin

loop

i1 -> x1

||

i2 -> x2

;

o1 <- x1

||

o2 <- x2

end

end

Syntax-directed Translation

Contents
• Introduction
• Synthesis of async circuits
• VLSI programming
• Logic synthesis
• Logic Synthesis into the Balsa flow
• Design flow
• Structural methods to fight the state explosion
• Structural Clustering based on Petri nets composition
• Experimental Results

Bus

Data

Transceiver

Device

D

DSr

VME Bus

Controller

LDS

DSw

LDTACK

DTACK

Logic Synthesis of async controllers

PETRI NET

Describe Behavior

Logic Synthesis of async controllers

Complete State Coding Conflicts

PETRI NET

STATE GRAPH

Enumerate States

Logic Synthesis of async controllers

Solve CSC (Petrify [Cortadella et al. 1996])

Logic Synthesis of async controllers

LOGIC EQUATIONS

lds = csc0 + d

d = ldtackcsc0

dtack = d

csc0 = dsr (csc0 + ldtack')

Synthesize (Petrify [Cortadella et al. 1996])