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Lab 6 SP601 Design Platform Introduction
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  1. Lab 6SP601 Design Platform Introduction FPGA Design Platform

  2. Introduction • FPGA SP601 設計板是Spartan-6系列中的理想入門用設計平台。 • 可利用Spartan-6 FPGA SP601來設計視聽娛樂、消費性電子以及一些低成本與低功耗的產品。 • SP601設計板功能包含乙太網路、通用I/O、 DDR2 memory control、Flash memory control以及UART等功能應用。

  3. SP601的特徵-1 • FPGA: XC6SLX16 CS324-2CES Spartan-6 • Configuration: • Onboard configuration circuitry • 8MB Quad SPI Flash • 16MB Parallel (BPI) Flash • JTAG

  4. SP601的特徵-2 • Memory: • DDR2 Component Memory 128MB • IIC 8Kb IIC EEPROM • Communication: • 10/100/1000 Tri-Speed Ethernet PHY • Serial (UART) to USB Bridge • Expansion Connectors: • FMC-LPC connector (68 single-ended or 34 differential user defined signals) • 8 User I/O (Digilent 2x6 Header)

  5. SP601的特徵-3 • Clocking: • 200MHz Oscillator (Differential) • Socket (Single-Ended) Populated with 27MHz Osc • SMA Connectors (Differential) • Display: • 4X LEDs • Control: • 4X Push Buttons • 4X DIP Switches

  6. SP601 Development Board

  7. SP601 Block Diagram

  8. Power Management • SP601是一個5V電源 供電,透過板子上的 滑動開關做電源開啟 或關閉,右圖為轉換 至板子上之電源供給 情形。

  9. User I/O • SP601提供了以下用戶和通用I/O能力,作為快速電路及裝置規劃做檢查或是做為基本的I/O • User LEDs • User DIP switch • Pushbutton switches • CPU Reset pushbutton switch • GPIO male pin header • FMC-LPC Connecter

  10. User LEDs 欲知其pin腳之詳細定義,請參照SP601 Hardware User Guide.pdfp30.31

  11. User DIP switch 欲知其FPGA pin腳之詳細定義,請參照SP601 Hardware User Guide.pdfp31

  12. Pushbutton switches 欲知其FPGA pin腳之詳細定義,請參照SP601 Hardware User Guide.pdfp32

  13. GPIO male pin header 欲知其FPGA pin腳之詳細定義,請參照SP601 Hardware User Guide.pdfp33

  14. JTAG Configuration • 透過USB-TO-JTAG來與電腦溝通。 • JTAG配置可以在任何模式下做設置並且在任何模式下都擁有優先權。

  15. Expansion Connector 欲知其FPGA pin腳之詳細定義,請參照SP601 Hardware User Guide.pdfp25.26.41

  16. Question and Answer 歷史人物中,誰跑最快?