Application Study of EAPR based Partial Dynamic Reconfiguration

1. Application Study of EAPR based Partial Dynamic Reconfiguration RCG Presentation (12/07/2007) Ramachandra Kallam

2. Outline Introduction Background Partial Dynamic Reconfiguration Iterative Repair Processor Results and Observations Conclusions Publications References

3. Introduction: Partial Reconfiguration Partial Reconfiguration: Static Partial Reconfiguration: Reconfiguring a portion of the device (changing the functionality) when the device is inactive without affecting other areas of the device Dynamic Partial Reconfiguration (PDR): Reconfiguring a portion of the device while the remaining design is still active and operating without affecting the remaining portion of the device.

4. Intuitive Benefits of using PDR Saves space on the FPGA Less time to change only a part of design Reduction of power dissipation by storing functionality to external memory Smaller FPGAs can be used to run an application

5. Applicability of PDR

6. NASA’s missions Space missions cannot rely on constant and reliable communication between earth and spacecraft On-board Processing FPGAs Low Cost compared to ASICs Reconfigurable Spacecraft event scheduling Iterative Repair and Simulated Annealing Iterative Repair Processor

7. Iterative Repair and Simulated Annealing Initial solution modified over several iterations Greedy Algorithm – may not yield optimal schedule (solution) Altering the solution randomly Evaluating the solution in a particular way Perfect solution? Different Solutions The way the initial solution is altered The way the solution is evaluated Different alter and evaluate stages

8. Spacecraft Event Scheduling A set of 100 events Need to find the best solution.

9. Different ‘Alter’ functions

10. Impact of ‘alter’ functions

11. Alternate ‘Evaluate’ functions Suppose a problem has three different tasks We can assign different weights to different tasks depending on the degree of importance of each task Can we store different ‘alter’ and ‘evaluate’ functions on the FPGA? Area constraints on the FPGA Solution?

12. PDR based on-board event scheduling

13. Lets review the definitions again: Partial Reconfiguration: Static Partial Reconfiguration: Reconfiguring a portion of the device (changing the functionality) when the device is inactive without affecting other areas of the device Dynamic Partial Reconfiguration (PDR): Reconfiguring a portion of the device while the remaining design is still active and operating without affecting the remaining portion of the device.

14. Background Method of Partial Reconfiguration Internal Configuration Access Port (ICAP) Bus Macros

15. Partial Reconfiguration Partial Reconfiguration is useful for systems with multiple functions that can time-share the same FPGA resources. TERMINOLOGY Reconfigurable Region (PRR) Reconfigurable Module (PRM) Static Logic Bus Macro Partial Bitstream Merged Bitstream

16. Literature "Run-time dynamic reconfiguration: a reality check based on FPGA architectures from Xilinx", Wu, K.; Madsen, J., NORCHIP Conference, 2005. 23rd, Vol., Iss., 21-22 Nov. 2005 Pages: 192- 195 "Study on column wise design compaction for reconfigurable systems", Kalte, H.; Lee, G.; Porrmann, M.; Ruckert, U., Field-Programmable Technology, 2004. Proceedings. 2004 IEEE International Conference on, Vol., Iss., 6-8 Dec. 2004 Pages: 413- 416 "Modular partial reconfigurable in Virtex FPGAs", Sedcole, P.; Blodget, B.; Anderson, J.; Lysaghi, P.; Becker, T., Field Programmable Logic and Applications, 2005. International Conference on, Vol., Iss., 24-26 Aug. 2005 Pages: 211- 216 "A Decade of Reconfigurable Computing: a Visionary Retrospective", Hartenstein, R., Design, Automation and Test in Europe, 2001. Conference and Exhibition 2001. Proceedings

17. Literature "Application-driven Research in Partial Reconfiguration", Juanjo Noguera, Robert Esser, Xilinx Research Labs “Two Flows for Partial Reconfiguration: Module Based or Difference Based”, Xilinx Research Labs "A new framework to accelerate Virtex-II Pro dynamic partial self-reconfiguration", Claus, C.; Muller, F.H.; Zeppenfeld, J.; Stechele, W., Parallel and Distributed Processing Symposium, 2007. IPDPS 2007. IEEE International "A lightweight approach for embedded reconfiguration of FPGAs", Blodget, B.; McMillan, S.; Lysaght, P., Design, Automation and Test in Europe Conference and Exhibition, 2003

18. Partial Reconfiguration Methods Module-based Partial Reconfiguration Systematic design of larger systems Modular Design Methodology Communication between modules is done through tri-state buffers Care should be taken that tri-state buffers are not being reconfigured High storage cost Long reconfiguration Latency Area-constrained placement and routing process. No hardware support to guarantee successful P&R

19. Partial Reconfiguration Methods Difference-based Partial Reconfiguration Suitable for very small designs Compares the circuit description of two designs, note the different frames between the two designs and creates a partial bitstream that only modifies the frames that are different The reconfiguration time and storage cost are proportional to number of frames that are different Very inefficient for large designs Both the designs have to be same at the layout level

20. Partial Reconfiguration Methods Early Access Partial Reconfiguration (EAPR) Similar to Modular-design methodology Allows Partial Reconfigurable regions of any rectangular size Allows signals in the base design to pass through PR region Placer will not locate any logic elements in PRR Router can route static nets through PRR Communication between static and partially reconfigurable region is done using slice-based (or LUT-based) bus macros

21. Medium for Partial Reconfiguration External – JTAG, UART (RS232) Internal – ICAP ICAP (Internal Configuration Access Port) Self-Reconfiguration controlled by soft-processor Internal read and write access to configuration logic Faster hwicap (provided by Xilinx) Wraps the ICAP with additional logic to read and write frames to BRAM Slave to OPB (On-chip Peripheral Bus)

22. ICAP - Flow Bitstream Flow Factors effecting Reconfiguration Time Bitstream length Bitstream transfer Ways to Improve Reduce the bitstream size (combitgen) Optimize the way the bitstreams are transferred

23. Bus Macros Bus Macros: Means of communication between PRMs and static design All connections between PRMs and static design must pass through a bus macro with the exception of a clock signal Type of Bus Macros Tri-state buffer (TBUF) based bus macros Slice-based (or LUT-based) bus macros Advantage of slice-based bus macros No signals lines should cross the border in partial reconfiguration TBUFs – will ignore the boundaries Slice-based – signals not crossing boundaries

24. Bus Macros All Bus Macros provide eight bits of data bandwidth and enable/disable control Provided with EAPR software tools as pre-placed and pre-routed with .nmc extension Expanded during NGDBuild Placement of Bus Macros Placed such that the bus macros are placed half on the static side and half in the PR Region Placed such that they do not straddle a DSP or BRAM column

25. Literature "An FPGA-Based Dynamically Reconfigurable Platform: From Concept to Realization", Mateusz Majer, Field Programmable Logic and Applications, 2006. FPL '06. International Conference on, Vol., Iss., Aug. 2006 Pages:1-2 Communicating with other modules is difficult as there may be routing through partial reconfigurable regions Proposed a new architecture for partial reconfiguration With the introduction of EAPR, it is possible to send static nets through partial reconfigurable regions

26. Literature "Modular partial reconfigurable in Virtex FPGAs", Sedcole, P.; Blodget, B.; Anderson, J.; Lysaghi, P.; Becker, T., Field Programmable Logic and Applications, 2005. International Conference on, Vol., Iss., 24-26 Aug. 2005 Pages: 211- 216 Apart from partial reconfiguration methods, this paper gives a analytical method to calculate reconfiguration time

27. Literature "Dynamic and Partial FPGA Exploitation", Jrgen Becker; Michael Hubner; Gerhard Hettich; Rainer Constapel; Joachim Eisenmann; Jrgen Luka, Proceedings of the IEEE, Vol.95, Iss.2, Feb. 2007 Pages:438-452 Motivation: electronics in automobiles are increasing with time. A Reconfigurable system for automotive industry to reduce the high number of control systems necessary for all the functions is presented

28. Literature "Dynamic loading of peripherals on reconfigurable system-on-chip", Yi Lu; Bergmann, N., Field-Programmable Technology, 2005. Proceedings. 2005 IEEE International Conference on, Vol., Iss., 11-14 Dec. 2005 Pages: 279- 280 Auto peripheral detection using partial dynamic self reconfiguration

29. Invoking Partial Dynamic Reconfiguration through Xilinx Early Access Partial Reconfiguration methodology

30. Early Access Partial Reconfiguration (EAPR) – Design Flow New Design flow by Xilinx in which slice based bus macros are used EAPR Design Flow HDL (Design Description) EDK (System level design) PlanAhead (Floor plan) Constraints (area, timing etc) Design Rule Check (DRC) Implement Static Design Implement PR Modules Create Bitstreams Programming the FPGA

31. Design Description HDL (Design Description) Have to decide which part of the design is to be implemented in static design Decide on number of PR regions Which functionality to implement (PRMs) in each PRR VHDL or Verilog Synthesis Keep Hierarchy Disable ‘Add I/O Buffers’ Set Global Clocks to ‘0’ (Figure of drc error)

32. Design Description Partial Reconfiguration Modules (PRMs) Pin Compatible Same port names

33. EDK (System Level Design) EDK (System Level Design) Create Peripherals Entity names should match System Architecture

34. EDK (System Level Design) Create software to run in Microblaze Create Netlist for the entire design Compile the software

35. PlanAhead (Floor Planning) PlanAhead (Floor Planning) Import system netlist

36. PlanAhead (Floor Planning) Set Constraints (area, location, timing)

37. PlanAhead (Floor Planning) Virtex-4 SX35 device with static and partial reconfigurable region

38. PlanAhead (Floor Planning) Set the Partial Reconfigurable Region (PRR) Add PRMs to the PRR

39. PlanAhead (Floor Planning) Design Rule Check (DRC)

40. PlanAhead (Floor Planning) ExploreAhead Static Runs PR Runs PRAssemble To create full and partial bitstreams

41. PAR of Full Design and PR Region

42. PlanAhead Some Disadvantages of PlanAhead Module has to be top level to set it as a reconfigurable region Cannot have gaps when specifying boundaries for a partial region

43. Programming the FPGA Programming the FPGA Export full bitstream to EDK Create SystemACE file Program the FPGA (file names should be small)

44. Test Application:ITERATIVE REPAIR PROCESSOR

45. Iterative Repair Processor Simulated Annealing consists of calling the same 5 functions repeatedly This structure has been exploited through use of a pipelined processor

46. System Architecture

47. Socket Bridge Communication between OPB and PRR using slice-based Bus Macros Capable of isolating PRR while Reconfiguration

48. PR of Iterative Repair Processor

49. Event Scheduling Short-term Mid-term Lon-term

50. Basic idea of setting up the system

51. Results & Observations

52. Results and Observations Partial Reconfiguration Observations Time for partial reconfiguration IR Processor Setup for Partial Reconfiguration Tested PR by reconfiguring with itself Ready for thermal capturing Partial Reconfiguration Tutorial

53. Partial Reconfiguration Latecny

54. Designs – ellintr_g and ellintr_d

55. Designs – ellintr_g and multiplier

56. Experimental vs. Analytical

57. IR Processor Time to Reconfigure the whole IR Processor: It takes 0.55 sec to reconfigure the whole processor If we reconfigure only two of the five stages in the Iterative Repair processor, the reconfiguration time will reduce significantly

58. CONCLUSIONS

59. Conclusions Current Status Ready to partial reconfigure the entire IR Processor Ready to test the IR Processor with thermal camera Need to set up IR Processor to reconfigure just two stages instead of the whole IR Processor Proposing a method to improve event scheduling in deep space missions using PDR Thesis defense in August?

60. Publications

61. Publications Journal Articles under review IET Transactions on Computers and Digital Techniques Phillips, J., Sudarsanam, A., Kallam, R., Carver, J., and Dasu, A., “Methodology to Derive Polymorphic Soft-IP Cores for FPGAs”

62. REFERENCES

63. References "An FPGA-Based Dynamically Reconfigurable Platform: From Concept to Realization", Mateusz Majer, Field Programmable Logic and Applications, 2006. FPL '06. International Conference on, Vol., Iss., Aug. 2006 Pages:1-2 "Run-time dynamic reconfiguration: a reality check based on FPGA architectures from Xilinx", Wu, K.; Madsen, J., NORCHIP Conference, 2005. 23rd, Vol., Iss., 21-22 Nov. 2005 Pages: 192- 195. "Partial and dynamic reconfiguration of FPGAs: a top down design methodology for an automatic implementation", Berthelot, F.; Nouvel, F., Emerging VLSI Technologies and Architectures, 2006. IEEE Computer Society Annual Symposium on, Vol.00, Iss., 2-3 March 2006 Pages: 2 pp. "Dynamic loading of peripherals on reconfigurable system-on-chip", Yi Lu; Bergmann, N., Field-Programmable Technology, 2005. Proceedings. 2005 IEEE International Conference on, Vol., Iss., 11-14 Dec. 2005 Pages: 279- 280

64. References "Dynamic and Partial FPGA Exploitation", Jrgen Becker; Michael Hubner; Gerhard Hettich; Rainer Constapel; Joachim Eisenmann; Jrgen Luka, Proceedings of the IEEE, Vol.95, Iss.2, Feb. 2007 Pages:438-452 "Study on column wise design compaction for reconfigurable systems", Kalte, H.; Lee, G.; Porrmann, M.; Ruckert, U., Field-Programmable Technology, 2004. Proceedings. 2004 IEEE International Conference on, Vol., Iss., 6-8 Dec. 2004 Pages: 413- 416 "Modular partial reconfigurable in Virtex FPGAs", Sedcole, P.; Blodget, B.; Anderson, J.; Lysaghi, P.; Becker, T., Field Programmable Logic and Applications, 2005. International Conference on, Vol., Iss., 24-26 Aug. 2005 Pages: 211- 216 "Partial Dynamic Reconfiguration: The Caronte Approach. A New Degree of Freedom in the HW/SW Codesign", Marco D. Santambrogio; Donatella Sciuto, Field Programmable Logic and Applications, 2006. FPL '06. International Conference on, Vol., Iss., Aug. 2006 ages:1-2

65. References "Fast IP-Core Generation in a Partial Dynamic Reconfiguration Workflow", Murgida, M.; Panella, A.; Rana, V.; Santambrogio, M.D.; Sciuto, D., Very Large Scale Integration, 2006 IFIP International Conference on, Vol., Iss., Oct. 2006 Pages:74-79 "A Decade of Reconfigurable Computing: a Visionary Retrospective", Hartenstein, R., Design, Automation and Test in Europe, 2001. Conference and Exhibition 2001. Proceedings "Application-driven Research in Partial Reconfiguration", Juanjo Noguera, Robert Esser, Xilinx Research Labs "A new framework to accelerate Virtex-II Pro dynamic partial self-reconfiguration", Claus, C.; Muller, F.H.; Zeppenfeld, J.; Stechele, W., Parallel and Distributed Processing Symposium, 2007. IPDPS 2007. IEEE International "A lightweight approach for embedded reconfiguration of FPGAs", Blodget, B.; McMillan, S.; Lysaght, P., Design, Automation and Test in Europe Conference and Exhibition, 2003

66. References "A Coarse-grain Pipelined Architecture for Accelerating Iterative Repair-Type Event Scheduling on SRAM-FPGAs", Jonathan Phillips and Aravind Dasu, VLSI Journal 2007 "ug070 - Virtex4 User guide", www.xilinx.com "ug071 - Virtex4 configuration guide",www.xilinx.com "Virtex Series Configuration Architecture User Guide", www.xilinx.com "Two Flows for Partial Reconfiguration: Module Based or Difference Based", www.xilinx.com "ug208- Early Access Partial Reconfigureation user guide", www.xilinx.com