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Design and VLSI implementation of a digital audio-specific DSP core for MP3/AAC

Design and VLSI implementation of a digital audio-specific DSP core for MP3/AAC. Kyoung Ho Bang, Nam Hun Jeong, Joon Seok Kim, Young Cheol Park and Dae Hee Youn IEEE Transactions on Consumer Electronics, 2002. page(s): 790 - 795 報告者 : 陳世偉 授課教師 : 黃英哲教授 92.03.24. Outline. Introduction

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Design and VLSI implementation of a digital audio-specific DSP core for MP3/AAC

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  1. Design and VLSI implementation of a digital audio-specific DSP core for MP3/AAC Kyoung Ho Bang, Nam Hun Jeong, Joon Seok Kim, Young Cheol Park and Dae Hee Youn IEEE Transactionson Consumer Electronics, 2002. page(s): 790 - 795 報告者: 陳世偉 授課教師:黃英哲教授 92.03.24

  2. Outline • Introduction • System architecture • Instruction set • System efficiency • Conclusion Seminar – Shi-Wei Chen

  3. Introduction • Standardized audio compression method • MP3 (MPEG1 layer3), AAC (Advanced Audio Coding) • The consumer market • High compression ratio • The transparent quality • Hardware performance are also rising. • DSP, ASIC, Microprocessor/Microcontroller Seminar – Shi-Wei Chen

  4. Comparison with CPUs DSP + ASIC + accelerator = digital audio-specific DSP core Seminar – Shi-Wei Chen

  5. Focus aspect Seminar – Shi-Wei Chen

  6. Audio-specific DSP feature • Data processing unit • 20-bit data, 48-bit ALU, accelerator • Multiplier : 20-bit × 20-bit • signed × signed, signed × unsigned, unsigned × unsigned • Convergent rounder, limiter • More than 18-bit PCM output • One cycle MAC for F/T transform processing • 2048 module addressing for management of 2048-size buffer of AAC • 512-point FFT for AC-3 and AAC Seminar – Shi-Wei Chen

  7. System architecture • 3-stage pipeline architecture • Instruction fetch stage • Instruction decode stage • Execution stage • One instruction/one clock cycle • Except branch instruction (2 clock cycles) • Harvard architecture • Program memory • Data memory • Load-Store architecture • MAC = MU + ALU Seminar – Shi-Wei Chen

  8. DSP architecture DSP Core Instruction Decoder Control signal Control signal Control signal Instruction Execution Unit D1 Bus Instruction Fetch Unit Data Processing Unit Data Addressing Generator Condition Code D2 Bus XAB XDB YAB YDB PMD PMA Program Memory X Data Memory Y Data Memory PMD : Program Memory Data Bus PMA : Program Memory Address Bus XAB : X Data Memory Address Bus XDB : X Data Memory Data Bus YAB : Y Data Memory Address Bus YDB : Y Data Memory Data Bus Seminar – Shi-Wei Chen

  9. Instruction set Special instructions : UNPACK, HUFFMAN Seminar – Shi-Wei Chen

  10. System efficiency • Design tool • VHDL • Compile and simulate tool • SYNOPSYS tool • 0.35μm, 3.3V COMOS technology • 40MHz Seminar – Shi-Wei Chen

  11. Quality test of MP3 ISO/IEC 13818-4 : NL < -101dB, MER : < 1 1.09 -100.3 NL : Noise level MER : Maximum error ratio Np : The number of processing bit No : The number of output PCM bit Seminar – Shi-Wei Chen

  12. Clock cycle for MP3 decoder Total sum 348,406 13.33 (40MHz / 48kHz sample rate) × 1152 = 960,000 cycles/frame Seminar – Shi-Wei Chen

  13. Memory requirement Seminar – Shi-Wei Chen

  14. Evaluation board Seminar – Shi-Wei Chen

  15. ？ Conclusion • The system consists of a 20-bit fixed-point DSP core for the software implementation and a hardware accelerator. • The decoding system can decode MP3 using only 13.33 MIPS with high efficiency. • The digital audio-specific DSP core is suitable for embedded system. Seminar – Shi-Wei Chen

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