Pipeline Synchronization Continued

1. Pipeline SynchronizationContinued This second part is based on the recent article Bridging Clock Domains by Synchronizing the Mice in the Mousetrap (PATMOS, Sep. 2003) by Joep Kessels and Ad PeetersPhilips Research Laboratories, The Netherlands together with Suk-Jin KimatKJIST, South Korea

2. A clk ME ME ME REQ ME ME ME ACK half cycle distance A clk B clk Recall Seizovic’s Synchronization Pipeline • Ripple Buffer between two clock domains • High throughput • Embedded synchronization • spanning a long distance  2-phase Bclk Seizovic, “Pipeline Synchronization,” Async 1994 Kessels, Peeters, Kim, "Bridging Clock Domains by synchronizing the mice in the mousetrap", PATMOS, 2003

3. Which buffer to use? • Ripple Buffer • Stream data (isochronous) • Throughput important, latency not • Steady rate maintained on both sides • Short distance (2-3 stages) • Pipe to improve throughput • or Long distance (many stages) • Improve throughput and bridge distance

4. Which buffer to use? • Pointer Buffer • Block data • Chunk available at-once • Rate not important • No sense to ripple every word in all pipe stages • Write few long bursts to SRAM and read on other side, with pointers • But if long distance, need Ripple

5. Outputs mutually exclusive : Connect ~clk and signal ‘R’ to inputs ‘A’ synced output, other output unused Today we refer to ME with ~clk as WAIT4 component S clk clk An ME as a Synchronizer X R1 A1 ME R A R0 A0

6. WAIT4 • A is synced to clk • Used in 4-phase, doesn’t sync A • used as building block for 2-phase sync

7. One Stage

8. “Mousetrap Cell” as FIFO Element • 2-phase single-rail • Any hi/lo signal toggleindicates change • reqǂack, sender cell is full • req=ack, data accepted by rcver, snder empty • “Equal” gate implements “empty” when req=ack • Cell empty  all 4 ctrl signals equal

9. MT Behavior • Ignoring ‘empty’ signal,MT similar to Muller Pipeline: ([Rreq=Rack * WreqǂRreq]; Rreq := Wreq)* (rcving cell empty)*(sending cell full); capture data, send ([WreqǂRack * WreqǂRreq]; Rreq := Wreq)* merely prevents idle operations ([WreqǂRack]; Rreq := Wreq)*

10. Mousetrap vs. Muller • Muller • Need to match delay of req to comb. logic • For 2-phase, need special Capture-Pass Latch • When full, every other cell contains data • Mousetrap • ‘empty’  no need for CP Latch • ‘empty’ does automatic delay-matching • When full, all cells contain data • No async elements (good for business)

11. 2)Rcver Ack back & Rreq forward 3) Rcver stores data 5) Rcver empties Latch EQ EQ+HoldLatch 4) Rcver gets Rack from outside 1) Snder Full • Rcver Ack to Snder does NOT indicate latch locked • Latch locked T(EQ+HoldLatch) after Ack • Timing restraint to ensure data not overrun

12. Delay Asymmetries • Delay of full/empty token • Full: T(Latch), Empty: T(Latch+EQ) • Phase-shift in handshake signals • FIFO at full speed is less than ½ full

13. Delay Asymmetries II • Different inputs of a cell have different delay-to-out • Connect slow EQ input to Ack to help timing, or • …to Req to improve performance

14. Delay Asymmetries III • Signals’ rising/falling edges have different transition delays • Req precedes empty,empty precedes Req • To avoid malfunction, ctrl-latch always slower than data-latch

15. UE4 • Parallel compositionof two WAIT4 ->Up-Edge 4-phase detector • Inv delay ensures 2nd WAIT4 closed before 1st opened • Use a FF here instead? • doesn’t filter out the metastability

16. UE2 • Detect up & down edges for 2-phase • Build a Edge 2-phase detector UE2 • ‘d’ ifferent, ‘e’mpty • ‘U’ even though it is up-and-down • Note resemblance to MT ctrl logic

17. Pipeline Interfaces • FIFO indicates ready : • To receive new Wdat: Wrdy • To send new valid Rdat: Rrdy • Environment enables: • Send of new valid Wdat: Wenb • Receive of new Rdat: Renb • Data transfer if both rdy and enb • Transfer item every clock

18. Read-Interface • Renb enables Rclk at FF • Z empty, Rrdy low, handshake signals equal • Z becomes full, Rrdy hi, handshakes differ • Upon next Rclk*Renb, FF makes handshakes equal again • Following Rclk*Renb, Z passes new Rdat • After T(Latch+EQ), X empties into Y • Handshaking continues … at next Rclk, state repeats itself

19. Write-Interface • Wenb enables Wclk at data+ctrl FF • ‘A’ full, handshake signals differ • ‘A’ empty, Wack toggles • Upon next Wclk*Wenb,‘A’ receives new Wdat • 1) C filled from B, ack from C waits at UE2 for Wclk • 2) After Wclk, B gets ack, ‘A’ filled from outside • 3) Handshaking continues … at next Wclk, state repeats itself

20. Integrated Synchronizing Circuit in MT Write Cell

21. Summary • Pipeline Synchronization • High throughput, embedded sync, long interconnect, 2-phase • The Mousetrap Cell • Synchronization components • WAIT4, UE4, UE2 • Buffer Interfaces • Write and Read sections • MT with integrated sync circuit