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Overview of Signed-Magnitude Arithmetic Operations in Computer Systems

This chapter delves into the fundamental arithmetic operations of signed-magnitude representation within computer systems, focusing on addition and subtraction. It covers various scenarios based on the comparison between two numbers, A and B, including actions when A is greater than, less than, or equal to B. The text provides detailed flowcharts and diagrams illustrating hardware implementations, such as parallel adders and sequence counters, alongside examples of binary multiplication and division. A comprehensive understanding is aimed at enhancing the efficiency of arithmetic computations in digital systems.

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Overview of Signed-Magnitude Arithmetic Operations in Computer Systems

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  1. CHAPTER 10 Computer Arithmetic

  2. Subtract Magnitudes Add Operation Magnitudes When A > b When A < B When A=B (+A) + (+B) +(A + B) (+A) + (-B) +(A - B) -(B - A) +(A - B) (-A) + (+B) -(A - B) +(B - A) +(A - B) (-A) + (-B) -(A + B) (+A) - (+B) +(A - B) -(B - A) +(A - B) (+A) - (-B) +(A + B) (-A) - (+B) -(A + B) (-A) - (-B) -(A - B) +(B - A) +(A - B) Table 10-1Addition and Subtraction of Signed-Magnitude numbers.

  3. Bs B register AVF Complementer M (Mode Control) Output Carry E Parallel adder S As A register Load Sum Figure 10-1Hardware for signed-magnitude addition and subtraction

  4. Subtract Operation Add Operation Minuend in A Subtrahend in B Augend in A Addend in B = 1 = 0 = 1 = 0 As ≠ Bs As ≠ Bs As = Bs EA ← A + B EA ← A + B +1 AVF ← E As Bs As Bs AVF ← E = 0 = 0 = 1 A≥B A E A<B A ← A ≠ 0 A ← 0 A ← A + 1 AS ← AS End (Result is in A and AS) Figure 10-2Flowchart for add and subtract operations. As = Bs

  5. BR Register Complementer and Parallel adder V Overflow AC Register Figure 10-3Hardware for signed 2’s complement addition and subtraction

  6. Subtract Add Minuend in AC Subtrahend in BR Augend in AC Addend in BR AC ← AC+BR + 1 V ← Overflow AC ← AC+BR V ← Overflow End End Figure 10-4Algorithm for adding and subtracting numbers in signed 2’s complement representation

  7. Bs B register Sequence counter (SC) Complement and parallel adder As Qs (rightmost bit) Qn 0 A register Q register E Figure 10-5Hardware for multiply operation.

  8. Multiply operation Multiplicand in B Multiplier in Q As←Qs Bs Qs ←Qs Bs A ← 0 , E ←0 SC ←n -1 =0 =1 Qn EA ← A + B Shr EAQ SC ← SC - 1 ≠0 =0 SC END (product is in AQ) Figure 10-6Flowchart for multiply operation.

  9. Multiplicand B= 10111 E A Q SC Multiplier in Q 0 00000 10011 101 Qn = 1 ; add B 10111 First partial product 0 10111 Shift right EAQ 0 01011 11001 100 Qn = 1 ; add B 10111 Second partial product 1 00010 Shift right EAQ 0 10001 01100 011 Qn = 0 ; shift right EAQ 0 01000 10110 010 Qn = 0 ; shift right EAQ 0 00100 01011 001 Qn = 1 ; add B 10111 First partial product 0 11011 Shift right EAQ 0 01101 10101 000 Final product in AQ = 0110110101 Table 10-2Numerical Example for Binary Multiplier.

  10. BR register Sequence counter (SC) Complement and parallel adder Qn Qn + 1 AC register QR register Figure 10-7Hardware for both algorithms.

  11. Multiply Multiplicand in BR Multiplier in QR AC ← 0 Qn+1 ← 0 SC ← n =10 =01 AC ← AC + BR + 1 AC ← AC + BR QnQn + 1 =00 =11 ashr (AC & QR) SC ← SC - 1 ≠0 =0 SC END Figure 10-8Both algorithms for multiplication of signed-2’s complement numbers.

  12. BR = 10111 Qn Qn + 1 Qn + 1 • Initial00000 10011 0 101 • 0 Subtract BR 01001 • 01001 • ashr 00100 11001 1 100 • 1 ashr 00010 01100 1 011 • 0 1 Add BR 10111 • 11001 • ashr 1110010110 0 010 • 0 0 ashr 11110 01011 0 001 • 0 Subtract BR 01001 • 00111 • ashr 00011 10101 1 000 Table 10-3Example of Multiplication with Booth Algorithm. Br + 1 = 01001 AC QR SC

  13. Figure 10-92-bit by 2-bit array multiplier. ao bo b1 b1 bo a1 bo b1 a1 ao ao ao bo b1 a1 a1 bo b1 c3 c2 c1 co HA C S HA C S c3 c2 c1 co

  14. b3 b2 b1 bo a1 b3 b2 b1 bo 0 Addend Augend 4-bit adder Sum and out put carry a2 b3 b2 b1 bo Addend Augend 4-bit adder Sum and out put carry c6 c5 c4 c3 c2 c1 co Figure 10-104-bit by 3-bit array multiplier. a0

  15. Divisor: B = 10001 11010 0111000000 01110 011100 - 10001 - 010110 - - 10001 - - 001010 - - - 010100 - - - - 10001 - - - - 000110 - - - - - 00110 Quotient = Q Dividend = A 5-bits of A < B, quotient has 5 bits 6-bits of A ≥ B Shift right B and subtract; enter 1 in Q 7-bits of remainder ≥ B Shift right B and subtract; enter 1 in Q Remainder < B; enter 0 in Q; shift right B Remainder ≥ B Shift right B and subtract; enter 1 in Q Remainder < B; enter 0 in Q Final remainder Figure 10-11Example of binary division

  16. Figure 10-12Example of binary division with digital hardware. Divisor B= 10001 B + 1 = 01111 E A Q SC Dividend: 01110 00000 5 shl EAQ 0 11100 00000 Add B +1 01111 E = 1 1 01011 Set Qn = 1 1 00101 00001 4 shl EAQ 0 10110 00010 Add B +1 01111

  17. Figure 10-13Flow chart for divide operation. Divide operation Dividend in AQ Divisor in B Divide magnitudes Qs← As Bs SC ← n - 1 Sh1 EAQ = 1 0 = E EA ← A+B+1 EA ← A + B + 1 A ← A + B + 1 = 1 = 0 E = 1 A < B E A ≥ B A ≥ B = 0 A < B EA ← A+B DVF ← 1 EA ← A+B DVF ← 0 Qn← 1 EA ← A + B SC ← SC - 1 ≠ 0 = 0 SC END Divide overflow END Quotient is in Q Remainder in A

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